This patch adds support for A320 development board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.
Signed-off-by: Po-Yu Chuang <ratb...@faraday-tech.com>
---
Index: Makefile
===================================================================
RCS file: /usr/local/cvsroot/ctd/u-boot-2009.06/Makefile,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 Makefile
--- Makefile 15 Jun 2009 06:47:34 -0000 1.1.1.1
+++ Makefile 23 Jun 2009 06:45:36 -0000
@@ -2940,6 +2940,13 @@
@$(MKCONFIG) $(@:_config=) arm s3c44b0 B2 dave
#########################################################################
+## Faraday A320 Systems
+#########################################################################
+
+a320_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t a320 faraday
+
+#########################################################################
## ARM720T Systems
#########################################################################
Index: board/faraday/a320/Makefile
===================================================================
RCS file: board/faraday/a320/Makefile
diff -N board/faraday/a320/Makefile
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/Makefile 16 Jun 2009 13:45:54 -0000 1.1
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := board.o timer.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
Index: board/faraday/a320/board.c
===================================================================
RCS file: board/faraday/a320/board.c
diff -N board/faraday/a320/board.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/board.c 23 Jun 2009 06:06:34 -0000 1.3
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <rtc.h>
+
+#include "ftsmc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FLASH_BANK0_CONFIG (FTSMC_BANK_ENABLE | \
+ FTSMC_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC_BANK_SIZE_1M | \
+ FTSMC_BANK_MBW_8)
+
+#define FLASH_BANK0_TIMING (FTSMC_TPR_RBE | \
+ FTSMC_TPR_AST(3) | \
+ FTSMC_TPR_CTW(3) | \
+ FTSMC_TPR_ATI(0xf) | \
+ FTSMC_TPR_AT2(3) | \
+ FTSMC_TPR_WTC(3) | \
+ FTSMC_TPR_AHT(3) | \
+ FTSMC_TPR_TRNA(0xf))
+
+#define FLASH_BANK1_CONFIG (FTSMC_BANK_ENABLE | \
+ FTSMC_BANK_BASE(PHYS_FLASH_2) | \
+ FTSMC_BANK_SIZE_32M | \
+ FTSMC_BANK_MBW_32 )
+
+#define FLASH_BANK1_TIMING (FTSMC_TPR_AST(3) | \
+ FTSMC_TPR_CTW(3) | \
+ FTSMC_TPR_ATI(0xf) | \
+ FTSMC_TPR_AT2(3) | \
+ FTSMC_TPR_WTC(3) | \
+ FTSMC_TPR_AHT(3) | \
+ FTSMC_TPR_TRNA(0xf))
+
+extern int timer_init (void);
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+static void
+ftsmc_setup_bank (int bank, unsigned int config, unsigned int timing)
+{
+ volatile struct ftsmc *smc = (struct ftsmc *)CONFIG_SYS_SMC_BASE;
+
+ if (bank < 0 || bank > 3) {
+ printf ("bank # %d invalid\n", bank);
+ return;
+ }
+
+ smc->bank[bank].cr = cpu_to_le32 (config);
+ smc->bank[bank].tpr = cpu_to_le32 (timing);
+}
+
+/* initialize Flash */
+static void ftsmc_init (void)
+{
+ ftsmc_setup_bank (0, FLASH_BANK0_CONFIG, FLASH_BANK0_TIMING);
+ ftsmc_setup_bank (1, FLASH_BANK1_CONFIG, FLASH_BANK1_TIMING);
+}
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
+
+ ftsmc_init ();
+ rtc_reset ();
+ timer_init ();
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_eth_init (bd_t * bd)
+{
+ return ftmac100_initialize (bd);
+}
+
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
+
+int interrupt_init (void)
+{
+ /* nothing happens here - we don't setup any IRQs */
+ return (0);
+}
Index: board/faraday/a320/config.mk
===================================================================
RCS file: board/faraday/a320/config.mk
diff -N board/faraday/a320/config.mk
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/config.mk 16 Jun 2009 13:45:54 -0000 1.1
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2009 Faraday Technology
+# Po-Yu Chuang <ratb...@faraday-tech.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
+#
+# see http://www.faraday-tech.com/ for more information
+
+# A320 has 1 bank of 64 MB DRAM (after remapped)
+#
+# 0000'0000 to 0400'0000
+#
+# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
+#
+# we load ourself to 03f8'0000
+#
+# download area is 0200'0000
+
+TEXT_BASE = 0x03f80000
Index: board/faraday/a320/ftahbc.h
===================================================================
RCS file: board/faraday/a320/ftahbc.h
diff -N board/faraday/a320/ftahbc.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/ftahbc.h 23 Jun 2009 06:08:57 -0000 1.2
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * AHB Controller
+ */
+#ifndef __FTAHBC
+#define __FTAHBC
+
+#define FTAHBC_OFFSET_SLAVE0_BSR 0x00
+#define FTAHBC_OFFSET_SLAVE1_BSR 0x04
+#define FTAHBC_OFFSET_SLAVE2_BSR 0x08
+#define FTAHBC_OFFSET_SLAVE3_BSR 0x0C
+#define FTAHBC_OFFSET_SLAVE4_BSR 0x10
+#define FTAHBC_OFFSET_SLAVE5_BSR 0x14
+#define FTAHBC_OFFSET_SLAVE6_BSR 0x18
+#define FTAHBC_OFFSET_SLAVE7_BSR 0x1C
+#define FTAHBC_OFFSET_SLAVE9_BSR 0x24
+#define FTAHBC_OFFSET_SLAVE12_BSR 0x30
+#define FTAHBC_OFFSET_SLAVE13_BSR 0x34
+#define FTAHBC_OFFSET_SLAVE14_BSR 0x38
+#define FTAHBC_OFFSET_SLAVE15_BSR 0x3C
+#define FTAHBC_OFFSET_SLAVE17_BSR 0x44
+#define FTAHBC_OFFSET_SLAVE18_BSR 0x48
+#define FTAHBC_OFFSET_SLAVE19_BSR 0x4C
+#define FTAHBC_OFFSET_SLAVE21_BSR 0x54
+#define FTAHBC_OFFSET_SLAVE22_BSR 0x58
+#define FTAHBC_OFFSET_PCR 0x80
+#define FTAHBC_OFFSET_TCR 0x84
+#define FTAHBC_OFFSET_ICR 0x88
+
+/*
+ * AHB Slave n Base/Size Register
+ */
+#define FTAHBC_BSR_BASE(x) ((x) & 0xfff00000)
+
+#define FTAHBC_BSR_SIZE_1M (0x0 << 16)
+#define FTAHBC_BSR_SIZE_2M (0x1 << 16)
+#define FTAHBC_BSR_SIZE_4M (0x2 << 16)
+#define FTAHBC_BSR_SIZE_8M (0x3 << 16)
+#define FTAHBC_BSR_SIZE_16M (0x4 << 16)
+#define FTAHBC_BSR_SIZE_32M (0x5 << 16)
+#define FTAHBC_BSR_SIZE_64M (0x6 << 16)
+#define FTAHBC_BSR_SIZE_128M (0x7 << 16)
+#define FTAHBC_BSR_SIZE_256M (0x8 << 16)
+#define FTAHBC_BSR_SIZE_512M (0x9 << 16)
+#define FTAHBC_BSR_SIZE_1G (0xa << 16)
+#define FTAHBC_BSR_SIZE_2G (0xb << 16)
+
+/*
+ * AHB Interrupt Control Register
+ */
+#define FTAHBC_ICR_REMAP (1 << 0)
+
+#endif /* __FTAHBC */
Index: board/faraday/a320/ftpmu.h
===================================================================
RCS file: board/faraday/a320/ftpmu.h
diff -N board/faraday/a320/ftpmu.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/ftpmu.h 23 Jun 2009 06:08:57 -0000 1.2
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU_H
+#define __FTPMU_H
+
+#define FTPMU_OFFSET_IDNMBR0 0x00
+#define FTPMU_OFFSET_OSCC 0x08
+#define FTPMU_OFFSET_PMODE 0x0C
+#define FTPMU_OFFSET_PMCR 0x10
+#define FTPMU_OFFSET_PED 0x14
+#define FTPMU_OFFSET_PEDSR 0x18
+#define FTPMU_OFFSET_PMSR 0x20
+#define FTPMU_OFFSET_PGSR 0x24
+#define FTPMU_OFFSET_MFPSR 0x28
+#define FTPMU_OFFSET_MISC 0x2C
+#define FTPMU_OFFSET_PDLLCR0 0x30
+#define FTPMU_OFFSET_PDLLCR1 0x34
+#define FTPMU_OFFSET_AHBMCLKOFF 0x38
+#define FTPMU_OFFSET_APBMCLKOFF 0x3C
+#define FTPMU_OFFSET_DCSRCR0 0x40
+#define FTPMU_OFFSET_DCSRCR1 0x44
+#define FTPMU_OFFSET_DCSRCR2 0x48
+#define FTPMU_OFFSET_SDRAMHTC 0x4C
+#define FTPMU_OFFSET_PSPR0 0x50
+#define FTPMU_OFFSET_PSPR1 0x54
+#define FTPMU_OFFSET_PSPR2 0x58
+#define FTPMU_OFFSET_PSPR3 0x5C
+#define FTPMU_OFFSET_PSPR4 0x60
+#define FTPMU_OFFSET_PSPR5 0x64
+#define FTPMU_OFFSET_PSPR6 0x68
+#define FTPMU_OFFSET_PSPR7 0x6C
+#define FTPMU_OFFSET_PSPR8 0x70
+#define FTPMU_OFFSET_PSPR9 0x74
+#define FTPMU_OFFSET_PSPR10 0x78
+#define FTPMU_OFFSET_PSPR11 0x7C
+#define FTPMU_OFFSET_PSPR12 0x80
+#define FTPMU_OFFSET_PSPR13 0x84
+#define FTPMU_OFFSET_PSPR14 0x88
+#define FTPMU_OFFSET_PSPR15 0x8C
+#define FTPMU_OFFSET_AHBDMA_RACCS 0x90
+#define FTPMU_OFFSET_JSS 0x9C
+#define FTPMU_OFFSET_CFC_RACC 0xA0
+#define FTPMU_OFFSET_SSP1_RACC 0xA4
+#define FTPMU_OFFSET_UART1TX_RACC 0xA8
+#define FTPMU_OFFSET_UART1RX_RACC 0xAC
+#define FTPMU_OFFSET_UART2TX_RACC 0xB0
+#define FTPMU_OFFSET_UART2RX_RACC 0xB4
+#define FTPMU_OFFSET_SDC_RACC 0xB8
+#define FTPMU_OFFSET_I2SAC97_RACC 0xBC
+#define FTPMU_OFFSET_IRDATX_RACC 0xC0
+#define FTPMU_OFFSET_USBD_RACC 0xC8
+#define FTPMU_OFFSET_IRDARX_RACC 0xCC
+#define FTPMU_OFFSET_IRDA_RACC 0xD0
+#define FTPMU_OFFSET_ED0_RACC 0xD4
+#define FTPMU_OFFSET_ED1_RACC 0xD8
+
+struct ftpmu {
+ unsigned int IDNMBR0; /* 0x00 */
+ unsigned int reserved0; /* 0x04 */
+ unsigned int OSCC; /* 0x08 */
+ unsigned int PMODE; /* 0x0C */
+ unsigned int PMCR; /* 0x10 */
+ unsigned int PED; /* 0x14 */
+ unsigned int PEDSR; /* 0x18 */
+ unsigned int reserved1; /* 0x1C */
+ unsigned int PMSR; /* 0x20 */
+ unsigned int PGSR; /* 0x24 */
+ unsigned int MFPSR; /* 0x28 */
+ unsigned int MISC; /* 0x2C */
+ unsigned int PDLLCR0; /* 0x30 */
+ unsigned int PDLLCR1; /* 0x34 */
+ unsigned int AHBMCLKOFF; /* 0x38 */
+ unsigned int APBMCLKOFF; /* 0x3C */
+ unsigned int DCSRCR0; /* 0x40 */
+ unsigned int DCSRCR1; /* 0x44 */
+ unsigned int DCSRCR2; /* 0x48 */
+ unsigned int SDRAMHTC; /* 0x4C */
+ unsigned int PSPR0; /* 0x50 */
+ unsigned int PSPR1; /* 0x54 */
+ unsigned int PSPR2; /* 0x58 */
+ unsigned int PSPR3; /* 0x5C */
+ unsigned int PSPR4; /* 0x60 */
+ unsigned int PSPR5; /* 0x64 */
+ unsigned int PSPR6; /* 0x68 */
+ unsigned int PSPR7; /* 0x6C */
+ unsigned int PSPR8; /* 0x70 */
+ unsigned int PSPR9; /* 0x74 */
+ unsigned int PSPR10; /* 0x78 */
+ unsigned int PSPR11; /* 0x7C */
+ unsigned int PSPR12; /* 0x80 */
+ unsigned int PSPR13; /* 0x84 */
+ unsigned int PSPR14; /* 0x88 */
+ unsigned int PSPR15; /* 0x8C */
+ unsigned int AHBDMA_RACCS; /* 0x90 */
+ unsigned int reserved2; /* 0x94 */
+ unsigned int reserved3; /* 0x98 */
+ unsigned int JSS; /* 0x9C */
+ unsigned int CFC_RACC; /* 0xA0 */
+ unsigned int SSP1_RACC; /* 0xA4 */
+ unsigned int UART1TX_RACC; /* 0xA8 */
+ unsigned int UART1RX_RACC; /* 0xAC */
+ unsigned int UART2TX_RACC; /* 0xB0 */
+ unsigned int UART2RX_RACC; /* 0xB4 */
+ unsigned int SDC_RACC; /* 0xB8 */
+ unsigned int I2SAC97_RACC; /* 0xBC */
+ unsigned int IRDATX_RACC; /* 0xC0 */
+ unsigned int reserved4; /* 0xC4 */
+ unsigned int USBD_RACC; /* 0xC8 */
+ unsigned int IRDARX_RACC; /* 0xCC */
+ unsigned int IRDA_RACC; /* 0xD0 */
+ unsigned int ED0_RACC; /* 0xD4 */
+ unsigned int ED1_RACC; /* 0xD8 */
+};
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU_ID_A320A 0x03200000
+#define FTPMU_ID_A320C 0x03200010
+#define FTPMU_ID_A320D 0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU_OSCC_OSCH_TRI (1 << 11)
+#define FTPMU_OSCC_OSCH_STABLE (1 << 9)
+#define FTPMU_OSCC_OSCH_OFF (1 << 8)
+
+#define FTPMU_OSCC_OSCL_TRI (1 << 3)
+#define FTPMU_RTCLSEL (1 << 2)
+#define FTPMU_OSCC_OSCL_STABLE (1 << 1)
+#define FTPMU_OSCC_OSCL_OFF (1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU_PMODE_DIVAHBCLK_MASK (0x7 << 4)
+#define FTPMU_PMODE_DIVAHBCLK_2 (0x0 << 4)
+#define FTPMU_PMODE_DIVAHBCLK_3 (0x1 << 4)
+#define FTPMU_PMODE_DIVAHBCLK_4 (0x2 << 4)
+#define FTPMU_PMODE_DIVAHBCLK_6 (0x3 << 4)
+#define FTPMU_PMODE_DIVAHBCLK_8 (0x4 << 4)
+#define FTPMU_PMODE_FCS (1 << 2)
+#define FTPMU_PMODE_TURBO (1 << 1)
+#define FTPMU_PMODE_SLEEP (1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU_PMSR_SMR (1 << 10)
+
+#define FTPMU_PMSR_RDH (1 << 2)
+#define FTPMU_PMSR_PH (1 << 1)
+#define FTPMU_PMSR_CKEHLOW (1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU_MFPSR_MODEMPINSEL (1 << 14)
+#define FTPMU_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU_MFPSR_AC97PINSEL (1 << 3)
+
+/*
+ * PLL/DLL Control Register 0
+ */
+#define FTPMU_PDLLCR0_PLL1NS(x) (((x) & 0x1ff) << 3)
+#define FTPMU_PDLLCR0_PLL1NS_VALUEOF(reg) (((reg) >> 3) & 0x1ff)
+#define FTPMU_PDLLCR0_PLL1DIS (1 << 0)
+
+#endif /* __FTPMU_H */
Index: board/faraday/a320/ftsdmc.h
===================================================================
RCS file: board/faraday/a320/ftsdmc.h
diff -N board/faraday/a320/ftsdmc.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/ftsdmc.h 23 Jun 2009 06:08:57 -0000 1.2
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC_H
+#define __FTSDMC_H
+
+#define FTSDMC_OFFSET_TP0 0x00
+#define FTSDMC_OFFSET_TP1 0x04
+#define FTSDMC_OFFSET_CR 0x08
+#define FTSDMC_OFFSET_BANK0_BSR 0x0C
+#define FTSDMC_OFFSET_BANK1_BSR 0x10
+#define FTSDMC_OFFSET_BANK2_BSR 0x14
+#define FTSDMC_OFFSET_BANK3_BSR 0x18
+#define FTSDMC_OFFSET_BANK4_BSR 0x1C
+#define FTSDMC_OFFSET_BANK5_BSR 0x20
+#define FTSDMC_OFFSET_BANK6_BSR 0x24
+#define FTSDMC_OFFSET_BANK7_BSR 0x28
+#define FTSDMC_OFFSET_ACR 0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC_TP0_TCL(x) ((x) & 0x3)
+#define FTSDMC_TP0_TWR(x) (((x) & 0x3) << 4)
+#define FTSDMC_TP0_TRF(x) (((x) & 0xf) << 8)
+#define FTSDMC_TP0_TRCD(x) (((x) & 0x7) << 12)
+#define FTSDMC_TP0_TRP(x) (((x) & 0xf) << 16)
+#define FTSDMC_TP0_TRAS(x) (((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC_TP1_REF_INTV(x) ((x) & 0xffff)
+#define FTSDMC_TP1_INI_REFT(x) (((x) & 0xf) << 16)
+#define FTSDMC_TP1_INI_PREC(x) (((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC_CR_SREF (1 << 0)
+#define FTSDMC_CR_PWDN (1 << 1)
+#define FTSDMC_CR_ISMR (1 << 2)
+#define FTSDMC_CR_IREF (1 << 3)
+#define FTSDMC_CR_IPREC (1 << 4)
+#define FTSDMC_CR_REFTYPE (1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC_BANK_ENABLE (1 << 28)
+
+#define FTSDMC_BANK_BASE(addr) (((addr) >> 20) << 16)
+
+#define FTSDMC_BANK_DDW_X4 (0 << 12)
+#define FTSDMC_BANK_DDW_X8 (1 << 12)
+#define FTSDMC_BANK_DDW_X16 (2 << 12)
+#define FTSDMC_BANK_DDW_X32 (3 << 12)
+
+#define FTSDMC_BANK_DSZ_16M (0 << 8)
+#define FTSDMC_BANK_DSZ_64M (1 << 8)
+#define FTSDMC_BANK_DSZ_128M (2 << 8)
+#define FTSDMC_BANK_DSZ_256M (3 << 8)
+
+#define FTSDMC_BANK_MBW_8 (0 << 4)
+#define FTSDMC_BANK_MBW_16 (1 << 4)
+#define FTSDMC_BANK_MBW_32 (2 << 4)
+
+#define FTSDMC_BANK_SIZE_1M 0x0
+#define FTSDMC_BANK_SIZE_2M 0x1
+#define FTSDMC_BANK_SIZE_4M 0x2
+#define FTSDMC_BANK_SIZE_8M 0x3
+#define FTSDMC_BANK_SIZE_16M 0x4
+#define FTSDMC_BANK_SIZE_32M 0x5
+#define FTSDMC_BANK_SIZE_64M 0x6
+#define FTSDMC_BANK_SIZE_128M 0x7
+#define FTSDMC_BANK_SIZE_256M 0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC_ACR_TOC(x) ((x) & 0x1f)
+#define FTSDMC_ACR_TOE (1 << 8)
+
+#endif /* __FTSDMC_H */
Index: board/faraday/a320/ftsmc.h
===================================================================
RCS file: board/faraday/a320/ftsmc.h
diff -N board/faraday/a320/ftsmc.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/ftsmc.h 23 Jun 2009 06:08:57 -0000 1.2
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC_H
+#define __FTSMC_H
+
+struct ftsmc {
+ struct {
+ unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
+ unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
+ } bank[4];
+ unsigned int pad[8]; /* 0x20 - 0x3c */
+ unsigned int ssr; /* 0x40 */
+};
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC_BANK_ENABLE (1 << 28)
+#define FTSMC_BANK_BASE(x) ((x) & 0x0fff1000)
+
+#define FTSMC_BANK_WPROT (1 << 11)
+
+#define FTSMC_BANK_SIZE_32K (0xb << 4)
+#define FTSMC_BANK_SIZE_64K (0xc << 4)
+#define FTSMC_BANK_SIZE_128K (0xd << 4)
+#define FTSMC_BANK_SIZE_256K (0xe << 4)
+#define FTSMC_BANK_SIZE_512K (0xf << 4)
+#define FTSMC_BANK_SIZE_1M (0x0 << 4)
+#define FTSMC_BANK_SIZE_2M (0x1 << 4)
+#define FTSMC_BANK_SIZE_4M (0x2 << 4)
+#define FTSMC_BANK_SIZE_8M (0x3 << 4)
+#define FTSMC_BANK_SIZE_16M (0x4 << 4)
+#define FTSMC_BANK_SIZE_32M (0x5 << 4)
+
+#define FTSMC_BANK_MBW_8 (0x0 << 0)
+#define FTSMC_BANK_MBW_16 (0x1 << 0)
+#define FTSMC_BANK_MBW_32 (0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC_TPR_ETRNA(x) (((x) & 0xf) << 28)
+#define FTSMC_TPR_EATI(x) (((x) & 0xf) << 24)
+#define FTSMC_TPR_RBE (1 << 20)
+#define FTSMC_TPR_AST(x) (((x) & 0x3) << 18)
+#define FTSMC_TPR_CTW(x) (((x) & 0x3) << 16)
+#define FTSMC_TPR_ATI(x) (((x) & 0xf) << 12)
+#define FTSMC_TPR_AT2(x) (((x) & 0x3) << 8)
+#define FTSMC_TPR_WTC(x) (((x) & 0x3) << 6)
+#define FTSMC_TPR_AHT(x) (((x) & 0x3) << 4)
+#define FTSMC_TPR_TRNA(x) (((x) & 0xf) << 0)
+
+#endif /* __FTSMC_H */
Index: board/faraday/a320/fttmr.h
===================================================================
RCS file: board/faraday/a320/fttmr.h
diff -N board/faraday/a320/fttmr.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/fttmr.h 23 Jun 2009 06:43:16 -0000 1.3
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR_H
+#define __FTTMR_H
+
+struct fttmr010 {
+ unsigned int timer1_counter; /* 0x00 */
+ unsigned int timer1_load; /* 0x04 */
+ unsigned int timer1_match1; /* 0x08 */
+ unsigned int timer1_match2; /* 0x0c */
+ unsigned int timer2_counter; /* 0x10 */
+ unsigned int timer2_load; /* 0x14 */
+ unsigned int timer2_match1; /* 0x18 */
+ unsigned int timer2_match2; /* 0x1c */
+ unsigned int timer3_counter; /* 0x20 */
+ unsigned int timer3_load; /* 0x24 */
+ unsigned int timer3_match1; /* 0x28 */
+ unsigned int timer3_match2; /* 0x2c */
+ unsigned int cr; /* 0x30 */
+ unsigned int interrupt_state; /* 0x34 */
+ unsigned int interrupt_mask; /* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR_TM3_UPDOWN (1 << 11)
+#define FTTMR_TM2_UPDOWN (1 << 10)
+#define FTTMR_TM1_UPDOWN (1 << 9)
+#define FTTMR_TM3_OFENABLE (1 << 8)
+#define FTTMR_TM3_CLOCK (1 << 7)
+#define FTTMR_TM3_ENABLE (1 << 6)
+#define FTTMR_TM2_OFENABLE (1 << 5)
+#define FTTMR_TM2_CLOCK (1 << 4)
+#define FTTMR_TM2_ENABLE (1 << 3)
+#define FTTMR_TM1_OFENABLE (1 << 2)
+#define FTTMR_TM1_CLOCK (1 << 1)
+#define FTTMR_TM1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR_TM3_OVERFLOW (1 << 8)
+#define FTTMR_TM3_MATCH2 (1 << 7)
+#define FTTMR_TM3_MATCH1 (1 << 6)
+#define FTTMR_TM2_OVERFLOW (1 << 5)
+#define FTTMR_TM2_MATCH2 (1 << 4)
+#define FTTMR_TM2_MATCH1 (1 << 3)
+#define FTTMR_TM1_OVERFLOW (1 << 2)
+#define FTTMR_TM1_MATCH2 (1 << 1)
+#define FTTMR_TM1_MATCH1 (1 << 0)
+
+#endif /* __FTTMR_H */
Index: board/faraday/a320/lowlevel_init.S
===================================================================
RCS file: board/faraday/a320/lowlevel_init.S
diff -N board/faraday/a320/lowlevel_init.S
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/lowlevel_init.S 23 Jun 2009 06:45:15 -0000 1.3
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <version.h>
+#include "ftahbc.h"
+#include "ftsdmc.h"
+
+/*
+ * Memory Mapping
+ */
+#define CONFIG_SYS_ROM_DEFAULT 0x00000000
+#define CONFIG_SYS_SDRAM_DEFAULT 0x10000000
+#define CONFIG_SYS_SDRAM_REMAPPED PHYS_SDRAM_1 /* remap location */
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num, rtmp1, rtmp2
+ mov \rtmp1, #\num
+ ldr \rtmp2, =CONFIG_SYS_DEBUG_LED
+ str \rtmp1, [\rtmp2]
+.endm
+
+.global reset_cpu
+reset_cpu:
+ b reset_cpu
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ led 0x0, r0, r1
+
+ /* if REMAP bit is set -> memory had been initialzed */
+
+ ldr r0, =CONFIG_SYS_AHBC_BASE
+ ldr r1, [r0, #FTAHBC_OFFSET_ICR]
+ tst r1, #FTAHBC_ICR_REMAP @ test REMAP bit
+ bne 1f
+
+ bl init_sdmc
+
+ led 0x1, r0, r1
+
+ /*
+ * copy U-Boot to RAM
+ */
+copy_code:
+ ldr r0, =CONFIG_SYS_ROM_DEFAULT /* r0 <- source address */
+ ldr r1, =CONFIG_SYS_SDRAM_DEFAULT /* r1 <- target address */
+
+ ldr r2, .LC5
+ ldr r3, .LC6
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+ led 0x2, r0, r1
+
+ bl remap
+1:
+ led 0x3, r0, r1
+
+ /* everything is fine now */
+ mov lr, r11
+ mov pc, lr
+
+.LC5:
+ .word _start
+.LC6:
+ .word __bss_start
+
+/*
+ * memory initialization
+ */
+init_sdmc:
+ mov r9, lr
+
+ /* set SDRAM register */
+ ldr r0, =CONFIG_SYS_SDMC_BASE
+ ldr r1, tp0
+ str r1, [r0, #FTSDMC_OFFSET_TP0]
+ ldr r1, tp1
+ str r1, [r0, #FTSDMC_OFFSET_TP1]
+
+ /* set to precharge */
+ mov r1, #FTSDMC_CR_IPREC
+ str r1, [r0, #FTSDMC_OFFSET_CR]
+
+ /* Waiting for SDRAM to set up */
+4:
+ ldr r1, [r0, #FTSDMC_OFFSET_CR]
+ cmp r1, #0
+ bne 4b
+
+ /* set mode register */
+ ldr r1, =FTSDMC_CR_ISMR
+ str r1, [r0, #FTSDMC_OFFSET_CR]
+
+ /* Waiting for SDRAM to set up */
+5:
+ ldr r1, [r0, #FTSDMC_OFFSET_CR]
+ cmp r1, #0
+ bne 5b
+
+ /* set to refresh */
+ mov r1, #FTSDMC_CR_IREF
+ str r1, [r0, #FTSDMC_OFFSET_CR]
+
+ /* Waiting for SDRAM to set up */
+6:
+ ldr r1, [r0, #FTSDMC_OFFSET_CR]
+ cmp r1, #0
+ bne 6b
+
+ ldr r1, b0_bsr
+ ldr r2, =FTSDMC_BANK_BASE(CONFIG_SYS_SDRAM_DEFAULT)
+ orr r1, r1, r2
+ str r1, [r0, #FTSDMC_OFFSET_BANK0_BSR] @ bank 0
+
+ ldr r1, =0x0
+ str r1, [r0, #FTSDMC_OFFSET_BANK1_BSR] @ bank 1 (clear/disable)
+ str r1, [r0, #FTSDMC_OFFSET_BANK2_BSR] @ bank 2 (clear/disable)
+ str r1, [r0, #FTSDMC_OFFSET_BANK3_BSR] @ bank 3 (clear/disable)
+ str r1, [r0, #FTSDMC_OFFSET_BANK4_BSR] @ bank 4 (clear/disable)
+ str r1, [r0, #FTSDMC_OFFSET_BANK5_BSR] @ bank 5 (clear/disable)
+ str r1, [r0, #FTSDMC_OFFSET_BANK6_BSR] @ bank 6 (clear/disable)
+ str r1, [r0, #FTSDMC_OFFSET_BANK7_BSR] @ bank 7 (clear/disable)
+
+ ldr r1, =FTSDMC_ACR_TOC(0x18)
+ str r1, [r0, #FTSDMC_OFFSET_ACR] @ arbiter
+
+ mov lr, r9
+ mov pc, lr
+
+/*
+ * This code will remap the memory ROM and SDRAM
+ * ROM will be placed on 0x80000000 SDRAM will jump to 0x0
+ */
+remap:
+ mov r9, lr
+
+ ldr r0, =CONFIG_SYS_SDMC_BASE
+
+ /* first adjust sdram */
+ ldr r1, b0_bsr
+ ldr r2, =FTSDMC_BANK_BASE(CONFIG_SYS_SDRAM_REMAPPED)
+ orr r1, r1, r2
+ str r1, [r0, #FTSDMC_OFFSET_BANK0_BSR] @ bank 0
+
+ /* then remap */
+ ldr r3, =CONFIG_SYS_AHBC_BASE
+ ldr r4, [r3, #FTAHBC_OFFSET_ICR]
+ orr r4, r4, #FTAHBC_ICR_REMAP @ Set REMAP bit
+ str r4, [r3, #FTAHBC_OFFSET_ICR]
+
+ mov lr, r9
+ mov pc, lr
+
+/*
+ * some parameters for the board
+ */
+tp0: .word FTSDMC_TP0_TRAS(2) | \
+ FTSDMC_TP0_TRP(1) | \
+ FTSDMC_TP0_TRCD(1) | \
+ FTSDMC_TP0_TRF(3) | \
+ FTSDMC_TP0_TWR(1) | \
+ FTSDMC_TP0_TCL(2)
+
+tp1: .word FTSDMC_TP1_INI_PREC(4) | \
+ FTSDMC_TP1_INI_REFT(8) | \
+ FTSDMC_TP1_REF_INTV(0x180)
+
+b0_bsr: .word FTSDMC_BANK_ENABLE | \
+ FTSDMC_BANK_DDW_X16 | \
+ FTSDMC_BANK_DSZ_256M | \
+ FTSDMC_BANK_MBW_32 | \
+ FTSDMC_BANK_SIZE_64M
+
+/*
+ * the literal pools origin
+ */
+ .ltorg
Index: board/faraday/a320/timer.c
===================================================================
RCS file: board/faraday/a320/timer.c
diff -N board/faraday/a320/timer.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/timer.c 23 Jun 2009 06:07:12 -0000 1.2
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include "ftpmu.h"
+#include "fttmr.h"
+
+static ulong timestamp;
+static ulong lastdec;
+
+static volatile struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_SYS_TIMERBASE;
+static volatile struct ftpmu *pmu = (struct ftpmu *)CONFIG_SYS_FTPMU_BASE;
+
+#define READ_TIMER (tmr->timer3_counter)
+#define TIMER_LOAD_VAL 0xffffffff
+
+int timer_init (void)
+{
+ debug ("%s()\n", __func__);
+
+ /* disable timers */
+ tmr->cr = 0;
+
+ /*
+ * use 32768Hz oscillator for RTC, WDT, TIMER
+ */
+
+ /* enable the 32768Hz oscillator */
+ pmu->OSCC &= ~(FTPMU_OSCC_OSCL_OFF | FTPMU_OSCC_OSCL_TRI);
+
+ /* wait until ready */
+ while (!(pmu->OSCC & FTPMU_OSCC_OSCL_STABLE)) ;
+
+ /* select 32768Hz oscillator */
+ pmu->OSCC |= FTPMU_RTCLSEL;
+
+ /* setup timer */
+ tmr->timer3_load = TIMER_LOAD_VAL;
+ tmr->timer3_counter = TIMER_LOAD_VAL;
+ tmr->timer3_match1 = 0;
+ tmr->timer3_match2 = 0;
+
+ /* we don't want timer to issue interrupts */
+ tmr->interrupt_mask = FTTMR_TM3_MATCH1
+ | FTTMR_TM3_MATCH2 | FTTMR_TM3_OVERFLOW;
+
+ tmr->cr |= FTTMR_TM3_CLOCK; /* use external clock */
+ tmr->cr |= FTTMR_TM3_ENABLE;
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked ();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked (void)
+{
+ lastdec = READ_TIMER; /* capure current decrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug ("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer (void)
+{
+ debug ("%s()\n", __func__);
+ reset_timer_masked ();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER; /* current tick value */
+
+ debug ("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug ("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer (ulong base)
+{
+ debug ("%s(%lx)\n", __func__, base);
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ debug ("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ debug ("%s(%lu)\n", __func__, usec);
+
+ if (usec >= 1000) {
+ /* if "big" number, spread normalization to seconds */
+
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ;
+
+ /* finish normalize. */
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000 * 1000);
+ }
+
+ endtime = get_timer_masked () + tmo;
+
+ debug ("%s(): endtime = %lx\n", __func__, endtime);
+
+ do {
+ ulong now = get_timer_masked ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+ debug ("%s(%lu)\n", __func__, usec);
+ udelay_masked (usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks (void)
+{
+ debug ("%s()\n", __func__);
+ return get_timer (0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ debug ("%s()\n", __func__);
+ tbclk = CONFIG_SYS_HZ;
+ return tbclk;
+}
Index: board/faraday/a320/u-boot.lds
===================================================================
RCS file: board/faraday/a320/u-boot.lds
diff -N board/faraday/a320/u-boot.lds
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ board/faraday/a320/u-boot.lds 18 Jun 2009 08:09:49 -0000 1.2
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <g...@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ _end = .;
+}
Index: include/configs/a320.h
===================================================================
RCS file: include/configs/a320.h
diff -N include/configs/a320.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ include/configs/a320.h 23 Jun 2009 06:25:54 -0000 1.3
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratb...@faraday-tech.com>
+ *
+ * Configuation settings for the Faraday A320 board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_A320 /* in a Faraday A320 SoC/Board */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*-----------------------------------------------------------------------
+ * Timer
+ */
+#define CONFIG_SYS_HZ 32768 /* timer ticks per second */
+#define CONFIG_SYS_TIMERBASE 0x98400000
+
+/*-----------------------------------------------------------------------
+ * RTC
+ */
+#define CONFIG_RTC_FTRTC
+#define CONFIG_SYS_RTC_BASE 0x98600000
+
+/*-----------------------------------------------------------------------
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 0x98200000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 18432000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_FTMAC100
+#define CONFIG_SYS_MAC100_BASE 0x90900000
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ETHADDR c3:10:da:ce:3f:3e
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.68.55
+#define CONFIG_SERVERIP 192.168.68.63
+
+/*-----------------------------------------------------------------------
+ * Hardware register bases
+ */
+#define CONFIG_SYS_AHBC_BASE 0x90100000 /* AHB Controller */
+#define CONFIG_SYS_SMC_BASE 0x90200000 /* Static Memory Controller */
+#define CONFIG_SYS_DEBUG_LED 0x902ffffc /* Debug LED */
+#define CONFIG_SYS_SDMC_BASE 0x90300000 /* SDRAM Controller */
+
+#define CONFIG_SYS_FTPMU_BASE 0x98100000 /* Power Management Unit */
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x02000000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END 0x03F00000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* no environments */
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x20000
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* support JEDEC */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+#define PHYS_FLASH_1 0x80000000
+#define PHYS_FLASH_2 0x80400000
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+
+#endif /* __CONFIG_H */
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