Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.

Signed-off-by: Simon Glass <s...@chromium.org>
---

 arch/x86/cpu/queensbay/tnc.c      | 27 ------------
 arch/x86/cpu/queensbay/tnc_pci.c  | 15 -------
 arch/x86/cpu/queensbay/topcliff.c | 32 +-------------
 arch/x86/include/asm/u-boot-x86.h | 17 ++++++++
 arch/x86/lib/fsp/Makefile         |  1 +
 arch/x86/lib/fsp/fsp_common.c     | 88 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 108 insertions(+), 72 deletions(-)
 create mode 100644 arch/x86/lib/fsp/fsp_common.c

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index f9b3bfa..30ab725 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -43,30 +43,3 @@ int arch_cpu_init(void)
 
        return 0;
 }
-
-int print_cpuinfo(void)
-{
-       post_code(POST_CPU_INFO);
-       return default_print_cpuinfo();
-}
-
-void reset_cpu(ulong addr)
-{
-       /* cold reset */
-       outb(0x06, PORT_RESET);
-}
-
-void board_final_cleanup(void)
-{
-       u32 status;
-
-       /* call into FspNotify */
-       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
-       status = fsp_notify(NULL, INIT_PHASE_BOOT);
-       if (status != FSP_SUCCESS)
-               debug("fail, error code %x\n", status);
-       else
-               debug("OK\n");
-
-       return;
-}
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
index 9b0b725..6c291f9 100644
--- a/arch/x86/cpu/queensbay/tnc_pci.c
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
 
        hose->region_count = 4;
 }
-
-int board_pci_post_scan(struct pci_controller *hose)
-{
-       u32 status;
-
-       /* call into FspNotify */
-       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
-       status = fsp_notify(NULL, INIT_PHASE_PCI);
-       if (status != FSP_SUCCESS)
-               debug("fail, error code %x\n", status);
-       else
-               debug("OK\n");
-
-       return 0;
-}
diff --git a/arch/x86/cpu/queensbay/topcliff.c 
b/arch/x86/cpu/queensbay/topcliff.c
index b01422a..25032cc 100644
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -5,43 +5,15 @@
  */
 
 #include <common.h>
-#include <errno.h>
-#include <malloc.h>
-#include <pci.h>
 #include <pci_ids.h>
-#include <sdhci.h>
 
 static struct pci_device_id mmc_supported[] = {
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
-       { }
 };
 
 int cpu_mmc_init(bd_t *bis)
 {
-       struct sdhci_host *mmc_host;
-       pci_dev_t devbusfn;
-       u32 iobase;
-       int ret;
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
-               devbusfn =  pci_find_devices(mmc_supported, i);
-               if (devbusfn == -1)
-                       return -ENODEV;
-
-               mmc_host = (struct sdhci_host *)malloc(sizeof(struct 
sdhci_host));
-               if (!mmc_host)
-                       return -ENOMEM;
-
-               mmc_host->name = "Topcliff SDHCI";
-               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
-               mmc_host->ioaddr = (void *)iobase;
-               mmc_host->quirks = 0;
-               ret = add_sdhci(mmc_host, 0, 0);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
+       return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
+                               ARRAY_SIZE(mmc_supported));
 }
diff --git a/arch/x86/include/asm/u-boot-x86.h 
b/arch/x86/include/asm/u-boot-x86.h
index b98afa8..44c24ff 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -45,6 +45,23 @@ ulong board_get_usable_ram_top(ulong total_size);
 void dram_init_banksize(void);
 int default_print_cpuinfo(void);
 
+struct pci_device_id;
+
+/**
+ * fsp_cpu_mmc_init() - set up PCI MMC devices
+ *
+ * This finds all the matching PCI IDs and sets them up as MMC devices.
+ *
+ * @name:              Name to use for devices
+ * @mmc_supported:     PCI IDs to search for
+ * @num_ids:           Number of elements in @mmc_supported
+ */
+int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
+                    int num_ids);
+
+/* Set up a UART which can be used with printch(), printhex8(), etc. */
+int setup_early_uart(void);
+
 void setup_pcat_compatibility(void);
 
 void isa_unmap_rom(u32 addr);
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 3a2bac0..5b12c12 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -5,5 +5,6 @@
 #
 
 obj-y += fsp_car.o
+obj-y += fsp_common.o
 obj-y += fsp_dram.o
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
new file mode 100644
index 0000000..846c136
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng...@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/fsp/fsp_support.h>
+
+int print_cpuinfo(void)
+{
+       post_code(POST_CPU_INFO);
+       return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+       /* cold reset */
+       outb(0x06, PORT_RESET);
+}
+
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+       u32 status;
+
+       /* call into FspNotify */
+       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+       status = fsp_notify(NULL, INIT_PHASE_PCI);
+       if (status != FSP_SUCCESS)
+               debug("fail, error code %x\n", status);
+       else
+               debug("OK\n");
+
+       return 0;
+}
+
+void board_final_cleanup(void)
+{
+       u32 status;
+
+       /* call into FspNotify */
+       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+       status = fsp_notify(NULL, INIT_PHASE_BOOT);
+       if (status != FSP_SUCCESS)
+               debug("fail, error code %x\n", status);
+       else
+               debug("OK\n");
+
+       return;
+}
+
+int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
+                    int num_ids)
+{
+       struct sdhci_host *mmc_host;
+       pci_dev_t devbusfn;
+       u32 iobase;
+       int ret;
+       int i;
+
+       for (i = 0; i < num_ids; i++) {
+               devbusfn = pci_find_devices(mmc_supported, i);
+               if (devbusfn == -1)
+                       return -ENODEV;
+
+               mmc_host = malloc(sizeof(struct sdhci_host));
+               if (!mmc_host)
+                       return -ENOMEM;
+
+               mmc_host->name = (char *)name;
+               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+               mmc_host->ioaddr = (void *)iobase;
+               mmc_host->quirks = 0;
+               ret = add_sdhci(mmc_host, 0, 0);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
-- 
2.2.0.rc0.207.ga3a616c

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