While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.
Make the single entry default and add a special
CONFIG_ARMV8_MULTIENTRY config option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.
This makes the Juno platform start U-Boot properly.
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
---
This patch applied on top of the other patch series send,
ending with
[PATCH 4/4] vexpress64: support the Juno Development Platform
Please apply it on top of these if the patch seems OK.
---
arch/arm/cpu/armv8/start.S | 8 ++++----
arch/arm/include/asm/macro.h | 8 ++++++++
board/armltd/vexpress64/vexpress64.c | 6 ------
include/configs/ls2085a_common.h | 5 +++++
include/configs/vexpress_aemv8a.h | 8 --------
5 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4f2227..9b439f30b779 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -77,6 +77,7 @@ reset:
/* Processor specific initialization */
bl lowlevel_init
+#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, master_cpu
/*
@@ -88,11 +89,10 @@ slave_cpu:
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
-
- /*
- * Master CPU
- */
master_cpu:
+ /* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
bl _main
/*-----------------------------------------------------------------------*/
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c4251ee0c..3b3146ab2239 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -78,6 +78,8 @@ lr .req x30
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg, mpidr_el1
tst \xreg, #0xff /* Test Affinity 0 */
b.ne \slave_label
@@ -90,6 +92,7 @@ lr .req x30
lsr \xreg, \xreg, #16
tst \xreg, #0xff /* Test Affinity 3 */
b.ne \slave_label
+#endif
.endm
/*
@@ -97,12 +100,17 @@ lr .req x30
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
+#else
+ b \master_label
+#endif
.endm
.macro armv8_switch_to_el2_m, xreg1
diff --git a/board/armltd/vexpress64/vexpress64.c
b/board/armltd/vexpress64/vexpress64.c
index 58973185ecda..7ab000cca77b 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -22,12 +22,6 @@ int board_init(void)
int dram_init(void)
{
- /*
- * Clear spin table so that secondary processors
- * observe the correct value after waken up from wfe.
- */
- *(unsigned long *)CPU_RELEASE_ADDR = 0;
-
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 6fe032c9ff64..7f6f6f34cfa4 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -8,6 +8,11 @@
#define __LS2_COMMON_H
#define CONFIG_SYS_GENERIC_BOARD
+/*
+ * These machines will enter U-Boot on the master CPU and also
+ * a secondary CPU, so we need to handle that.
+ */
+#define CONFIG_ARMV8_MULTIENTRY
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LSCH3
diff --git a/include/configs/vexpress_aemv8a.h
b/include/configs/vexpress_aemv8a.h
index 7fb28a54ba17..e276fff7e442 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -56,14 +56,6 @@
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
-/* SMP Spin Table Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
-#else
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#endif
-
/* CS register bases for the original memory map. */
#define V2M_PA_CS0 0x00000000
#define V2M_PA_CS1 0x14000000
--
1.9.3
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