[U-Boot] [PATCH 2/2] arm: ls102xa: Fix interleaving issue on CCI400 slave interface S2

[Alison Wang]

On silicon VER1.0, there is an interleaving issue on CCI400
slave interface S2. The workaround is to enable regulation
of outstanding read transactions for slave interface S2.

Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
 board/freescale/ls1021aqds/ls1021aqds.c           | 7 +++++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 7 +++++++
 3 files changed, 16 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 4b1cd3b..1a61d4a 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -463,6 +463,8 @@ struct ccsr_ddr {
 #define CCI400_SHAORD_NON_SHAREABLE    0x00000002
 #define CCI400_DVM_MESSAGE_REQ_EN      0x00000002
 #define CCI400_SNOOP_REQ_EN            0x00000001
+#define CCI400_REGULATION_READ_EN      0x00000008
+#define CCI400_INT_MAX_OUT_TRANS       0x01000000
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index b6bba6c..93df046 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -217,6 +217,13 @@ int board_early_init_f(void)
                 */
                out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
                out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+               /*
+                * To fix interleaving issue on VER1.0, regulation of
+                * outstanding read transactions for slave interface S2
+                * is enabled
+                */
+               out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN);
+               out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS);
 
                /* Workaround for the issue that DDR could not respond to
                 * barrier transaction which is generated by executing DSB/ISB
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index bd6068f..9101bd6 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -301,6 +301,13 @@ int board_early_init_f(void)
                 */
                out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
                out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+               /*
+                * To fix interleaving issue on VER1.0, regulation of
+                * outstanding read transactions for slave interface S2
+                * is enabled
+                */
+               out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN);
+               out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS);
        }
 
        return 0;
-- 
2.1.0.27.g96db324

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