On Mon, Feb 16, 2015 at 10:15:56AM +0530, Lokesh Vutla wrote: > The value in SDRAM_REF_CTRL controls the delay time between > the initial rising edge of DDR_RESETn to rising edge of DDR_CKE > (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL > should be written with a value corresponding to 500us delay before > starting DDR initialization sequence, and configure proper > value at the end of sequence. > > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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