Hi,
On 20-02-15 09:15, Siarhei Siamashka wrote:
On Thu, 19 Feb 2015 14:59:16 +0100
Hans de Goede <[email protected]> wrote:
Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
halving the mbus frequency, so set it to 300 MHz ourselves and base the
mbus divider on that.
Signed-off-by: Hans de Goede <[email protected]>
---
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index d297ed0..c28ee05 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -144,7 +144,16 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0xa1005000
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT 0xa1009900
+#else
#define PLL6_CFG_DEFAULT 0xa1009911
+#endif
/* nand clock */
#define NAND_CLK_SRC_OSC24 0
Are there any good reasons to use 600MHz instead of 300MHz for PLL6 in
the default u-boot build?
Maybe PLL6 can be just set to 300MHz for sun5i in all cases, regardless
of the CONFIG_OLD_SUNXI_KERNEL_COMPAT define?
Basically the reasons are the same as why you want to keep PLL5 running
at a high speed, PLL6 is a potential parent PLL for all mod0 clk using
peripherals, and having it higher gives us more possible clocks.
I agree that this (and the PLL5 speed) are an issue we need a better fix
for then CONFIG_OLD_SUNXI_KERNEL_COMPAT if at all possible.
I'll discuss this further as a reply to your:
"[PATCH] sunxi: Machine id hack to prevent loading buggy sunxi-3.4 kernels"
mail.
Regards,
Hans
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