Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon <n...@ti.com>
---
arch/arm/cpu/armv7/omap3/board.c | 16 ----------------
include/configs/ti_omap3_common.h | 6 ++++++
2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 7ce30949a6c6..cc3a43341335 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */
extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif
@@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
-
#ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate L2-cache from secure mode */
omap3_invalidate_l2_cache_secure();
@@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32
clear_bits)
}
}
-static void omap3_setup_aux_cr(void)
-{
- /* Workaround for Cortex-A8 errata: #454179 #430973
- * Set "IBE" bit
- * Set "Disable Branch Size Mispredicts" bit
- * Workaround for erratum #621766
- * Enable L1NEON bit
- * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
- */
- omap3_update_aux_cr_secure(0xE0, 0);
-}
-
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
diff --git a/include/configs/ti_omap3_common.h
b/include/configs/ti_omap3_common.h
index f909f6b94a18..db15c12ddf53 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -27,6 +27,12 @@
# define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
#endif
+/* Common ARM Erratas */
+#define CONFIG_ARM_ARCH_CP15_ERRATA
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
+
/* The chip has SDRC controller */
#define CONFIG_SDRC
--
1.7.9.5
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