From: Dinh Nguyen <dingu...@opensource.altera.com>
Add the calls in the spl_board_init to enable SDRAM, timer, and UART.
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
Acked-by: Marek Vasut <ma...@denx.de>
---
arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index bd9f338..b123336 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -145,6 +145,10 @@ void spl_board_init(void)
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
+ socfpga_sdram_enable();
+ socfpga_uart0_enable();
+ socfpga_osc1timer_enable();
+
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
cm_basic_init(&cm_default_cfg);
--
2.2.1
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