On Tue, Feb 17, 2015 at 05:08:37PM +0100, Michal Sojka wrote: > From: Michal Sojka <so...@merica.cz> > > Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of > WAIT0 pin for determining whether the NAND is ready or not. This only > works if all NAND chips are connected to WAIT0. If some chips are > connected to the other available pin WAIT1, nand_wait() does not really > wait and prints a WARN_ON message. > > This patch allows the board to provide configuration of which chip is > connected to which WAITx signal. For example, one can define in > include/configs/foo.h: > > #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1 > > This would mean that chips using to CS0 and 1 are connected to WAIT0 and > chips with CS2 and 3 are connected to WAIT1. > > Signed-off-by: Michal Sojka <so...@merica.cz> > Acked-by: Stefan Roese <s...@denx.de> > Tested-by: Michal Vokáč <michal.vo...@comap.cz> > > Cc: Tom Rini <tr...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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