The timer clock is system clock divided by 4, not fixed 12MHz. This is
common to the SoC, not board specific.
Signed-off-by: York Sun <york...@freescale.com>
---
README | 8 ++++++++
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24 ++++++++++++++++++++++++
board/freescale/ls2085a/ls2085a.c | 18 ------------------
include/configs/ls2085a_common.h | 6 +++++-
4 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/README b/README
index f473515..776ebf4 100644
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
+
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
+
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd147..e985181 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
return 0;
}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+ unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+ /* Enable timebase for all clusters.
+ * It is safe to do so even some clusters are not enabled.
+ */
+ out_le32(cltbenr, 0xf);
+
+ /* Enable clock for timer
+ * This is a global setting.
+ */
+ out_le32(cntcr, 0x1);
+
+ return 0;
+}
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,24 +55,6 @@ int dram_init(void)
return 0;
}
-int timer_init(void)
-{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
- u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
-
- /* Enable timebase for all clusters.
- * It is safe to do so even some clusters are not enabled.
- */
- out_le32(cltbenr, 0xf);
-
- /* Enable clock for timer
- * This is a global setting.
- */
- out_le32(cntcr, 0x1);
-
- return 0;
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 339337d..b47cf68 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -72,7 +72,11 @@
#define CONFIG_DP_DDR_NUM_CTRLS 1
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 12000000 /* 12MHz */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
--
1.7.9.5
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