On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding <tred...@nvidia.com>
>
> For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
> but should be written as 1.
>
> For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
>
> Cc: Albert Aribaud <albert.u.b...@aribaud.net>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Signed-off-by: Thierry Reding <tred...@nvidia.com>
> ---
> arch/arm/cpu/armv8/cache_v8.c | 6 +++---
> arch/arm/include/asm/armv8/mmu.h | 4 ++++
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 254a629a3b8c..f9b04057f696 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -50,15 +50,15 @@ static void mmu_setup(void)
> el = current_el();
> if (el == 1) {
> set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> - TCR_FLAGS | TCR_EL1_IPS_BITS,
> + TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
> MEMORY_ATTRIBUTES);
> } else if (el == 2) {
> set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> - TCR_FLAGS | TCR_EL2_IPS_BITS,
> + TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
> MEMORY_ATTRIBUTES);
> } else {
> set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> - TCR_FLAGS | TCR_EL3_IPS_BITS,
> + TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
> MEMORY_ATTRIBUTES);
> }
> /* enable the mmu */
> diff --git a/arch/arm/include/asm/armv8/mmu.h
> b/arch/arm/include/asm/armv8/mmu.h
> index 6d42f5533a74..8e577b34e4ba 100644
> --- a/arch/arm/include/asm/armv8/mmu.h
> +++ b/arch/arm/include/asm/armv8/mmu.h
> @@ -109,6 +109,10 @@
> TCR_IRGN_WBWA | \
> TCR_T0SZ(VA_BITS))
>
> +#define TCR_EL1_RSVD (1 << 31)
> +#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
> +#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
> +
> #ifndef __ASSEMBLY__
> void set_pgtable_section(u64 *page_table, u64 index,
> u64 section, u64 memory_type);
>
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
M.
--
Jazz is not dead. It just smells funny...
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