This erratum requires setting GLITCH_EN bit in debug register.
Signed-off-by: York Sun <york...@freescale.com>
CC: Heiko Schocher <h...@denx.de>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
Add comment to I2C workaround
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index ca00108..7cbf43c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -37,11 +37,45 @@ static void erratum_rcw_src(void)
#endif
}
+#define I2C_DEBUG_REG 0x6
+#define I2C_GLITCH_EN 0x8
+/*
+ * This erratum indicates setting glitch_en bit enables
+ * digital glitch filter for improved stability.
+ */
+static void erratum_i2c(void)
+{
+ u8 __iomem *ptr;
+#ifdef CONFIG_SYS_I2C
+#ifdef I2C1_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C2_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C3_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C4_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#endif
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
+ erratum_i2c();
}
#ifdef CONFIG_SPL_BUILD
--
1.7.9.5
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