On Wednesday, March 25, 2015 at 03:07:34 AM, Stephen Warren wrote: > The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a > VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally > access DRAM via this same L2 cache (although they always bypass the L1 > cache). Peripherals select whether to use or bypass the cache via the > top two bits of the bus address. > > An IOMMU exists between the ARM CPU and the rest of the system. This > controls whether the ARM CPU's accesses use or bypass the L1 and/or L2 > cache. This IOMMU is configured/controlled exclusively by the VideoCore > CPU. > > In order for DRAM accesses made by the ARM core to be coherent with > accesses made by other DMA peripherals, we must program a bus address > into those peripherals that causes the peripheral's accesses to use the > same set of caches that the ARM core's accesses will use. > > On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of > the L2 cache. This corresponds to addresses based at 0x40000000. > > On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of > the L2 cache. This corresponds to addresses based at 0xc0000000. > > This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according > to those rules. > > For full details of this setup, please see Dom Cobley's description at: > http://lists.denx.de/pipermail/u-boot/2015-March/208201.html > http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038 > https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html > > Signed-off-by: Stephen Warren <swar...@wwwdotorg.org>
Applied to -next, thanks! Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot