The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for kernel for T1024/T1040/T2080. To enable it,
define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: Yangbo Lu <yangbo...@freescale.com>
Cc: York Sun <york...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/speed.c | 49 ++++++++++++++++++++++++++++++-
arch/powerpc/include/asm/config_mpc85xx.h | 10 +++++--
drivers/mmc/fsl_esdhc.c | 5 ++++
include/e500.h | 1 +
4 files changed, 62 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7e69873..79202bb 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -69,7 +69,8 @@ void get_sys_info(sys_info_t *sys_info)
[14] = 4, /* CC4 PPL / 4 */
};
uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@@ -313,6 +314,48 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#endif
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_PPC_T2080)
+#define ESDHC_CLK_SEL 0x00000007
+#define ESDHC_CLK_SHIFT 0
+#define ESDHC_CLK_RCWSR 15
+#else /* Support T1040 T1024 by now */
+#define ESDHC_CLK_SEL 0xe0000000
+#define ESDHC_CLK_SHIFT 29
+#define ESDHC_CLK_RCWSR 7
+#endif
+ rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
+ switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
+ break;
+ case 2:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
+ break;
+#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
+ case 4:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
+ break;
+#if defined(CONFIG_PPC_T2080)
+ case 5:
+ sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
+ break;
+#endif
+ case 6:
+ sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
+ break;
+ case 7:
+ sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
+ break;
+#endif
+ default:
+ sys_info->freq_sdhc = 0;
+ printf("Error: Unknown SDHC peripheral clock select!\n");
+ }
+#endif
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
@@ -520,12 +563,16 @@ int get_clocks (void)
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
+#else
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
defined(CONFIG_P1014)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
+#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 01b0905..24c593b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -757,7 +757,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
@@ -773,6 +772,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
+ per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -805,7 +807,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
@@ -818,6 +819,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
+ per rcw field value */
#define CONFIG_QBMAN_CLK_DIV 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@@ -865,6 +868,9 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
+ per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 355cada..8dea365 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -689,8 +689,13 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
}
#endif
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+ gd->arch.sdhc_clk, 1);
+#else
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
gd->arch.sdhc_clk, 1);
+#endif
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
do_fixup_by_compat_u32(blob, compat, "adapter-type",
(u32)(gd->arch.sdhc_adapter), 1);
diff --git a/include/e500.h b/include/e500.h
index 5884a22..07d0ee8 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -15,6 +15,7 @@ typedef struct
unsigned long freq_ddrbus;
unsigned long freq_localbus;
unsigned long freq_qe;
+ unsigned long freq_sdhc;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif
--
2.1.0.27.g96db324
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