From: Stefan Roese <s...@denx.de>
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.
Signed-off-by: Stefan Roese <s...@denx.de>
Signed-off-by: Kevin Smith <kevin.sm...@elecsyscorp.com>
---
arch/arm/mach-mvebu/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 04681fc..417fc35 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
+#include <asm/pl310.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
@@ -240,6 +241,13 @@ int cpu_eth_init(bd_t *bis)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ /* First disable L2 cache - may still be enable from BootROM */
+ if (mvebu_soc_family() == MVEBU_SOC_A38X)
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
--
2.3.2
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