Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh <ramneek.mehr...@freescale.com>
---
drivers/usb/host/xhci-keystone.c | 88 ----------------------------------------
include/configs/ks2_evm.h | 1 +
2 files changed, 1 insertion(+), 88 deletions(-)
diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c
index 05d338f..924fb76 100644
--- a/drivers/usb/host/xhci-keystone.c
+++ b/drivers/usb/host/xhci-keystone.c
@@ -68,94 +68,6 @@ static void keystone_xhci_phy_unset(struct keystone_xhci_phy
*phy)
writel(val, &phy->phy_clock);
}
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-
- /* Assert USB3 PHY reset */
- setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 revision, val;
- unsigned long t_rst;
- unsigned int dwc3_hwparams1;
-
- revision = readl(&dwc3_reg->g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
- puts("this is not a DesignWare USB3 DRD Core\n");
- return -EINVAL;
- }
-
- /* issue device SoftReset too */
- writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl);
-
- t_rst = get_timer(0);
- do {
- val = readl(&dwc3_reg->d_ctl);
- if (!(val & DWC3_DCTL_CSFTRST))
- break;
- WATCHDOG_RESET();
- } while (get_timer(t_rst) < 500);
-
- if (val & DWC3_DCTL_CSFTRST) {
- debug("Reset timed out\n");
- return -2;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
-
- val = readl(&dwc3_reg->g_ctl);
- val &= ~DWC3_GCTL_SCALEDOWN_MASK;
- val &= ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- val &= ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- printf("No power optimization available\n");
- }
-
- /*
- * WORKAROUND: DWC3 revisions <1.90a have a bug
- * where the device can fail to connect at SuperSpeed
- * and falls back to high-speed mode which causes
- * the device to enter a Connect/Disconnect loop
- */
- if ((revision & DWC3_REVISION_MASK) < 0x190a)
- val |= DWC3_GCTL_U2RSTECN;
-
- writel(val, &dwc3_reg->g_ctl);
-
- return 0;
-}
-
static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
{
int ret;
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 42280ca..58730b2 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -197,6 +197,7 @@
/* USB Configuration */
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
--
1.8.3.1
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