mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kue...@gmail.com> Cc: Tom Rini <tr...@konsulko.com> Cc: Matthew Starr <mst...@hedonline.com> Cc: Andrej Rosano <and...@inversepath.com> Cc: Stefano Babic <sba...@denx.de> Cc: Chris Kuethe <chris.kue...@gmail.com> Cc: Fabio Estevam <feste...@gmail.com> Cc: Marek Vasut <ma...@denx.de> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 -- GDB has a 'break' feature; why doesn't it have 'fix' too? _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot