Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2:
- Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to
match the order in Kconfig
arch/x86/dts/crownbay.dts | 20 ++++++++++++++++++++
configs/crownbay_defconfig | 4 ++++
2 files changed, 24 insertions(+)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index d68efda..1ec90cd 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -23,6 +23,26 @@
silent_console = <0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d3a370d..d21177d 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -2,6 +2,10 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_TARGET_CROWNBAY=y
+CONFIG_SMP=y
+CONFIG_MAX_CPUS=2
CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_CMD_CPU=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
+CONFIG_CPU=y
--
1.8.2.1
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