Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too.
Signed-off-by: Tom Warren <twar...@nvidia.com>
---
arch/arm/include/asm/arch-tegra/ap.h | 6 +--
arch/arm/include/asm/arch-tegra/clk_rst.h | 28 +++++++++++---
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 3 +-
arch/arm/include/asm/arch-tegra/pmc.h | 7 ++--
arch/arm/include/asm/arch-tegra/tegra.h | 4 +-
arch/arm/mach-tegra/Kconfig | 12 ++++++
arch/arm/mach-tegra/Makefile | 5 ++-
arch/arm/mach-tegra/ap.c | 9 ++++-
arch/arm/mach-tegra/clock.c | 3 +-
arch/arm/mach-tegra/cpu.c | 55 ++++++++++++++++++++--------
arch/arm/mach-tegra/cpu.h | 10 +++--
include/fdtdec.h | 3 ++
lib/fdtdec.c | 2 +
13 files changed, 111 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/ap.h
b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e..76773b7 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -24,8 +24,6 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM 0x40000000
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
/* Do chip-specific vpr config */
void config_vpr(void);
#else
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index de50e08..43efa65 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
+ TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
- uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
+ uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
+ uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
+ uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
+
+ uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
+ uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
+ uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
+
+ uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
- /* Additional (T114) registers */
+ /* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7]; /* 0x574-58c */
struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
- u32 _rsrv32_2[25];
- /* Tegra124 */
- uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+ /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+ /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+ uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
+ /*
+ * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+ * two later if PLLA1 is needed, but for now this is cleaner.
+ */
+ uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
index 7a86acb..695f3e6 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2012
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -21,5 +21,6 @@
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
#define CHIPID_TEGRA124 0x40
+#define CHIPID_TEGRA210 0x21
#endif /* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h
b/arch/arm/include/asm/arch-tegra/pmc.h
index 1dd3154..66c0879 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011,2014
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -294,6 +294,7 @@ struct pmc_ctlr {
#define CRAIL 0
#define CE0 14
#define C0NC 15
+#define SOR 17
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
@@ -303,7 +304,7 @@ struct pmc_ctlr {
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
-#elif defined(CONFIG_TEGRA124)
+#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 3
@@ -314,7 +315,7 @@ struct pmc_ctlr {
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define MULT_16 4
#endif
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h
b/arch/arm/include/asm/arch-tegra/tegra.h
index d63af0e..b6c7cab 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -74,6 +74,7 @@ enum {
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
+ SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
};
/*
@@ -88,6 +89,7 @@ enum {
TEGRA_SOC_T30,
TEGRA_SOC_T114,
TEGRA_SOC_T124,
+ TEGRA_SOC_T210,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 7494f8d..38f9d09 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -60,6 +60,17 @@ config TEGRA124
select DM_SPI
select DM_GPIO
+config TEGRA210
+ bool "Tegra210 family"
+ select OF_CONTROL
+ select ARM64
+ select DM
+ select DM_SPI_FLASH
+ select DM_SERIAL
+ select DM_I2C
+ select DM_SPI
+ select DM_GPIO
+
endchoice
config SYS_MALLOC_F_LEN
@@ -69,5 +80,6 @@ source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
+source "arch/arm/mach-tegra/tegra210/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index fefc180..0db8ee0 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2010,2011 Nvidia Corporation.
+# (C) Copyright 2010-2015 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -24,7 +24,9 @@ obj-y += pinmux-common.o
obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
obj-$(CONFIG_TEGRA124) += vpr.o
+obj-$(CONFIG_TEGRA210) += vpr.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
@@ -35,3 +37,4 @@ obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index 7b89c01..ee84967 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -1,5 +1,5 @@
/*
-* (C) Copyright 2010-2014
+* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -92,6 +92,13 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_T124;
}
break;
+ case CHIPID_TEGRA210:
+ switch (sku_id) {
+ case SKU_ID_T210_ENG:
+ default:
+ return TEGRA_SOC_T210;
+ }
+ break;
}
/* unknown chip/sku id */
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 24047b8..992bc41 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -634,6 +634,7 @@ static void set_avp_clock_source(u32 src)
/*
* This function is useful on Tegra30, and any later SoCs that have compatible
* PLLP configuration registers.
+ * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
*/
void tegra30_set_up_pllp(void)
{
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index c6f3b02..f7d45e8 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,7 @@ int get_num_cpus(void)
{
struct apb_misc_gp_ctlr *gp;
uint rev;
+ debug("%s entry\n", __func__);
gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
@@ -39,6 +40,8 @@ int get_num_cpus(void)
break;
case CHIPID_TEGRA30:
case CHIPID_TEGRA114:
+ case CHIPID_TEGRA124:
+ case CHIPID_TEGRA210:
default:
return 4;
break;
@@ -128,13 +131,30 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
+
+ /*
+ * T210: 700 MHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 24:20 5
+ * PLLX_BASE n 15: 8 8
+ * PLLX_BASE m 7: 0 8
+ */
+ {
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
+ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
+ },
};
static inline void pllx_set_iddq(void)
{
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
+ debug("%s entry\n", __func__);
/* Disable IDDQ */
reg = readl(&clkrst->crc_pllx_misc3);
@@ -151,15 +171,14 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn,
u32 divm,
{
int chip = tegra_get_chip();
u32 reg;
+ debug("%s entry\n", __func__);
/* If PLLX is already enabled, just return */
if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
- debug("pllx_set_rate: PLLX already enabled, returning\n");
+ debug("%s: PLLX already enabled, returning\n", __func__);
return 0;
}
- debug(" pllx_set_rate entry\n");
-
pllx_set_iddq();
/* Set BYPASS, m, n and p to PLLX_BASE */
@@ -182,19 +201,19 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn,
u32 divm,
reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base = 0x%08X\n", reg);
+ debug("%s: base = 0x%08X\n", __func__, reg);
/* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc);
- debug("pllx_set_rate: misc = 0x%08X\n", reg);
+ debug("%s: misc = 0x%08X\n", __func__, reg);
/* Enable PLLX last, once it's all configured */
reg = readl(&pll->pll_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base final = 0x%08X\n", reg);
+ debug("%s: base final = 0x%08X\n", __func__, reg);
return 0;
}
@@ -206,24 +225,23 @@ void init_pllx(void)
int soc_type, sku_info, chip_sku;
enum clock_osc_freq osc;
struct clk_pll_table *sel;
-
- debug("init_pllx entry\n");
+ debug("%s entry\n", __func__);
/* get SOC (chip) type */
soc_type = tegra_get_chip();
- debug(" init_pllx: SoC = 0x%02X\n", soc_type);
+ debug("%s: SoC = 0x%02X\n", __func__, soc_type);
/* get SKU info */
sku_info = tegra_get_sku_info();
- debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
+ debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
/* get chip SKU, combo of the above info */
chip_sku = tegra_get_chip_sku();
- debug(" init_pllx: Chip SKU = %d\n", chip_sku);
+ debug("%s: Chip SKU = %d\n", __func__, chip_sku);
/* get osc freq */
osc = clock_get_osc_freq();
- debug(" init_pllx: osc = %d\n", osc);
+ debug("%s: osc = %d\n", __func__, osc);
/* set pllx */
sel = &tegra_pll_x_table[chip_sku][osc];
@@ -234,6 +252,7 @@ void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 clk;
+ debug("%s entry\n", __func__);
/*
* NOTE:
@@ -282,6 +301,7 @@ static void remove_cpu_io_clamps(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
+ debug("%s entry\n", __func__);
/* Remove the clamps on the CPU I/O signals */
reg = readl(&pmc->pmc_remove_clamping);
@@ -297,6 +317,7 @@ void powerup_cpu(void)
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
+ debug("%s entry\n", __func__);
if (!is_cpu_powered()) {
/* Toggle the CPU power state (OFF -> ON) */
@@ -336,7 +357,7 @@ void reset_A9_cpu(int reset)
int num_cpus = get_num_cpus();
int cpu;
- debug("reset_a9_cpu entry\n");
+ debug("%s entry\n", __func__);
/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
for (cpu = 1; cpu < num_cpus; cpu++)
reset_cmplx_set_enable(cpu, mask, 1);
@@ -350,7 +371,7 @@ void clock_enable_coresight(int enable)
{
u32 rst, src = 2;
- debug("clock_enable_coresight entry\n");
+ debug("%s entry\n", __func__);
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
@@ -377,6 +398,8 @@ void clock_enable_coresight(int enable)
void halt_avp(void)
{
+ debug("%s entry\n", __func__);
+
for (;;) {
writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
FLOW_CTLR_HALT_COP_EVENTS);
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h
index b4ca44f..3f38969 100644
--- a/arch/arm/mach-tegra/cpu.h
+++ b/arch/arm/mach-tegra/cpu.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2014
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -14,7 +14,7 @@
#define NVBL_PLLP_KHZ 216000
#define CSITE_KHZ 144000
#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
- defined(CONFIG_TEGRA124)
+ defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define NVBL_PLLP_KHZ 408000
#define CSITE_KHZ 204000
#else
@@ -35,7 +35,7 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
+#define CORESIGHT_UNLOCK 0xC5ACCE55
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
@@ -53,6 +53,10 @@
#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
+#define SB_AA64_RESET_LOW 0x6000C230
+#define SB_AA64_RESET_HIGH 0x6000C234
+
struct clk_pll_table {
u16 n;
u16 m;
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 2323603..4b3f8d1 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -137,6 +137,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
@@ -145,6 +146,8 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
/* Tegra124 XUSB pad controller */
+ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+ /* Tegra210 XUSB pad controller */
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c0c471d..3eef250 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -31,6 +31,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
@@ -38,6 +39,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"),
COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"),
COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
+ COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
--
1.8.2.1.610.g562af5b
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