Acked-by: Ruchika Gupta<ruchika.gu...@freescale.com>
> -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:43 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 2/3] crypto/fsl - change starting entropy delay value > > Ruchika, > > Please comment/ack this patch and others in this set. > > York > > On 05/05/2015 06:48 AM, Alex Porosanu wrote: > > The entropy delay (the length in system clocks of each entropy sample) > > for the RNG4 block of CAAM is dependent on the frequency of the SoC. > > By elaborate methods, it has been determined that a good starting > > value for all platforms integrating the CAAM IP is 3200. Using a > > higher value has additional benefit of speeding up the process of > > instantiating the RNG, since the entropy delay will be increased and > > instantiation of the RNG state handles will be reattempted by the > > driver. If the starting value is low, for certain platforms, this can > > lead to a quite lengthy process. > > This patch changes the starting value of the length of the entropy > > sample to 3200 system clocks. > > In addition to this change, the attempted entropy delay values are now > > printed on the console upon initialization of the RNG block. > > > > Signed-off-by: Alex Porosanu <alexandru.poros...@freescale.com> > > --- > > include/fsl_sec.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/include/fsl_sec.h b/include/fsl_sec.h index > > 14f6633..c84b6ad 100644 > > --- a/include/fsl_sec.h > > +++ b/include/fsl_sec.h > > @@ -35,7 +35,7 @@ struct rng4tst { > > u32 rtmctl; /* misc. control register */ > > u32 rtscmisc; /* statistical check misc. register */ > > u32 rtpkrrng; /* poker range register */ > > -#define RTSDCTL_ENT_DLY_MIN 1200 > > +#define RTSDCTL_ENT_DLY_MIN 3200 > > #define RTSDCTL_ENT_DLY_MAX 12800 > > union { > > u32 rtpkrmax; /* PRGM=1: poker max. limit register */ > > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot