Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Luka Perkov <luka.per...@sartura.hr>
---
v2:
- Use clrsetbits_le32()
arch/arm/mach-mvebu/cpu.c | 3 +++
arch/arm/mach-mvebu/include/mach/soc.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 23c2a97..fa82067 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -241,6 +241,9 @@ int arch_cpu_init(void)
*/
mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+ /* Disable MBUS error propagation */
+ clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
+
return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index 71254c5..a29e5dc 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -66,6 +66,9 @@
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
+#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
+#define MBUS_ERR_PROP_EN (1 << 8)
+
#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
--
2.4.6
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
