The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: Alexander Stein <alexander...@web.de> Acked-by: Stephen Warren <swar...@wwwdotorg.org> Tested-by: Stephen Warren <swar...@wwwdotorg.org> --- Changes in v4: * Set CONFIG_SYS_CACHELINE_SIZE for rpi and rpi2 separately as they differ include/configs/rpi.h | 2 ++ include/configs/rpi_2.h | 1 + 2 files changed, 3 insertions(+) diff --git a/include/configs/rpi.h b/include/configs/rpi.h index ab2f4db..86422e3 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -7,6 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 32 + #include "rpi-common.h" #endif diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h index 2e7e74f..13dc8de 100644 --- a/include/configs/rpi_2.h +++ b/include/configs/rpi_2.h @@ -9,6 +9,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BCM2836 +#define CONFIG_SYS_CACHELINE_SIZE 64 #include "rpi-common.h" -- 2.4.6 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot