On Tue, Jul 21, 2015 at 1:15 AM, Peng Fan <peng....@freescale.com> wrote:
> Follow linux dma flow:
> Before DMA read, be sure to invalidate the cache over the address
> range of DMA buffer to prevent cache coherency problems.
> After DMA read, invalidate dcache again.
>
> Signed-off-by: Peng Fan <peng....@freescale.com>
> Acked-by: Marek Vasut <ma...@denx.de>
> ---
>
> Changes v2:
> Add Marek's Acked by
>
> drivers/mtd/nand/mxs_nand.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
> index 97011b2..f15cf36 100644
> --- a/drivers/mtd/nand/mxs_nand.c
> +++ b/drivers/mtd/nand/mxs_nand.c
> @@ -469,6 +469,9 @@ static void mxs_nand_read_buf(struct mtd_info *mtd,
> uint8_t *buf, int length)
>
> mxs_dma_desc_append(channel, d);
>
> + /* Invalidate caches */
> + mxs_nand_inval_data_buf(nand_info);
> +
> /* Execute the DMA chain. */
> ret = mxs_dma_go(channel);
> if (ret) {
> @@ -635,6 +638,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd,
> struct nand_chip *nand,
>
> mxs_dma_desc_append(channel, d);
>
> + /* Invalidate caches */
> + mxs_nand_inval_data_buf(nand_info);
> +
> /* Execute the DMA chain. */
> ret = mxs_dma_go(channel);
> if (ret) {
> --
> 1.8.4
>
Acked-by: Tim Harvey <thar...@gateworks.com>
This resolves an issue I've been digging into regarding IMX6 NAND read failures.
Tim
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
