As the updated microcode-tool doesn't write dts properties into the microcode dtsi files, update the existing dtsi and board dts files to keep sync with the tool. Note for FSP based boards, add a new property "intel,fsp-parser" which indicates it will be consumed by Intel FSP and the properties for a single microcode are removed.
Signed-off-by: Bin Meng <bmeng...@gmail.com> --- arch/x86/dts/bayleybay.dts | 5 +++++ arch/x86/dts/chromebook_link.dts | 11 +++++++++++ arch/x86/dts/crownbay.dts | 5 +++++ arch/x86/dts/microcode/m0130673322.dtsi | 23 ++++++++++++----------- arch/x86/dts/microcode/m0220661105_cv.dtsi | 23 ++++++++++++----------- arch/x86/dts/microcode/m0230671117.dtsi | 23 ++++++++++++----------- arch/x86/dts/microcode/m12206a7_00000029.dtsi | 25 ++++++++++++++----------- arch/x86/dts/microcode/m12306a9_0000001b.dtsi | 25 ++++++++++++++----------- arch/x86/dts/minnowmax.dts | 5 +++++ 9 files changed, 90 insertions(+), 55 deletions(-) diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 0ca7c3e..ea27537 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -230,7 +230,12 @@ microcode { update@0 { + compatible = "intel,microcode"; + intel,fsp-parser; + + data = < #include "microcode/m0230671117.dtsi" + >; }; }; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index ad390bf..b5cea9d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -239,7 +239,18 @@ microcode { update@0 { + compatible = "intel,microcode"; + intel,header-version = <1>; + intel,update-revision = <0x1b>; + intel,date-code = <0x5292014>; + intel,processor-signature = <0x306a9>; + intel,checksum = <0x579ae07a>; + intel,loader-revision = <1>; + intel,processor-flags = <0x12>; + + data = < #include "microcode/m12306a9_0000001b.dtsi" + >; }; }; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 3af9cc3..6b36c87 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -83,7 +83,12 @@ microcode { update@0 { + compatible = "intel,microcode"; + intel,fsp-parser; + + data = < #include "microcode/m0220661105_cv.dtsi" + >; }; }; diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi index 90bf2fb..0482397 100644 --- a/arch/x86/dts/microcode/m0130673322.dtsi +++ b/arch/x86/dts/microcode/m0130673322.dtsi @@ -4,19 +4,21 @@ * node. * * Date: + * + * Device tree properties for this microcode: + * + * compatible = "intel,microcode"; + * intel,header-version = <1>; + * intel,update-revision = <0x322>; + * intel,date-code = <0x4012014>; + * intel,processor-signature = <0x30673>; + * intel,checksum = <0x17b0d914>; + * intel,loader-revision = <1>; + * intel,processor-flags = <0x1>; */ -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x322>; -intel,date-code = <0x4012014>; -intel,processor-signature = <0x30673>; -intel,checksum = <0x17b0d914>; -intel,loader-revision = <1>; -intel,processor-flags = <0x1>; - /* The first 48-bytes are the public header which repeats the above data */ -data = < + 0x01000000 0x22030000 0x14200104 0x73060300 0x14d9b017 0x01000000 0x01000000 0xd0cb0000 0x00cc0000 0x00000000 0x00000000 0x00000000 @@ -3281,4 +3283,3 @@ data = < 0x1e176b9c 0xe3fcb69f 0x17a2eee9 0xa9e6467f 0xbf6b0246 0x6a08c0fb 0x7fb943b6 0xb8f67c0e 0x2b3b4ffc 0xb155d20c 0x4eb5de53 0xf078715b - >; diff --git a/arch/x86/dts/microcode/m0220661105_cv.dtsi b/arch/x86/dts/microcode/m0220661105_cv.dtsi index ada8bfc..b2f7642 100644 --- a/arch/x86/dts/microcode/m0220661105_cv.dtsi +++ b/arch/x86/dts/microcode/m0220661105_cv.dtsi @@ -32,19 +32,21 @@ * node. * * Date: Sat Sep 13 22:51:38 CST 2014 + * + * Device tree properties for this microcode: + * + * compatible = "intel,microcode"; + * intel,header-version = <1>; + * intel,update-revision = <0x105>; + * intel,date-code = <0x7182011>; + * intel,processor-signature = <0x20661>; + * intel,checksum = <0x52558795>; + * intel,loader-revision = <1>; + * intel,processor-flags = <0x2>; */ -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x105>; -intel,date-code = <0x7182011>; -intel,processor-signature = <0x20661>; -intel,checksum = <0x52558795>; -intel,loader-revision = <1>; -intel,processor-flags = <0x2>; - /* The first 48-bytes are the public header which repeats the above data */ -data = < + 0x01000000 0x05010000 0x11201807 0x61060200 0x95875552 0x01000000 0x02000000 0xd0130000 0x00140000 0x00000000 0x00000000 0x00000000 @@ -365,4 +367,3 @@ data = < 0x8ba4f1e8 0xfbd4c592 0xb678c884 0xff3be2f1 0xca013570 0xfb0598df 0x3cb9cc1d 0xe3ba8ca3 0xc3d7ecee 0x0ae84a0b 0x0d70f0c3 0x963110ff - >; diff --git a/arch/x86/dts/microcode/m0230671117.dtsi b/arch/x86/dts/microcode/m0230671117.dtsi index 439e84a..24322fb 100644 --- a/arch/x86/dts/microcode/m0230671117.dtsi +++ b/arch/x86/dts/microcode/m0230671117.dtsi @@ -4,19 +4,21 @@ * node. * * Date: + * + * Device tree properties for this microcode: + * + * compatible = "intel,microcode"; + * intel,header-version = <1>; + * intel,update-revision = <0x117>; + * intel,date-code = <0x4102013>; + * intel,processor-signature = <0x30671>; + * intel,checksum = <0x2abfd907>; + * intel,loader-revision = <1>; + * intel,processor-flags = <0x2>; */ -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x117>; -intel,date-code = <0x4102013>; -intel,processor-signature = <0x30671>; -intel,checksum = <0x2abfd907>; -intel,loader-revision = <1>; -intel,processor-flags = <0x2>; - /* The first 48-bytes are the public header which repeats the above data */ -data = < + 0x01000000 0x17010000 0x13201004 0x71060300 0x07d9bf2a 0x01000000 0x02000000 0xd0070100 0x00080100 0x00000000 0x00000000 0x00000000 @@ -4241,4 +4243,3 @@ data = < 0x0d5094b7 0xe01beae3 0x98a56a78 0x26c2da3b 0xba4fd221 0xbe0f8666 0x61146fe5 0x1278a21e 0x6dbcfa62 0xb46f9dc4 0x5e21fc7d 0x58c634f0 - >; diff --git a/arch/x86/dts/microcode/m12206a7_00000029.dtsi b/arch/x86/dts/microcode/m12206a7_00000029.dtsi index fe888bf..8142725 100644 --- a/arch/x86/dts/microcode/m12206a7_00000029.dtsi +++ b/arch/x86/dts/microcode/m12206a7_00000029.dtsi @@ -30,19 +30,23 @@ * --- * This is a device tree fragment. Use #include to add these properties to a * node. + * + * Date: Sat Sep 13 22:51:38 CST 2014 + * + * Device tree properties for this microcode: + * + * compatible = "intel,microcode"; + * intel,header-version = <1>; + * intel,update-revision = <0x29>; + * intel,date-code = <0x6122013>; + * intel,processor-signature = <0x206a7>; + * intel,checksum = <0xc9c91df0>; + * intel,loader-revision = <1>; + * intel,processor-flags = <0x12>; */ -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x29>; -intel,date-code = <0x6122013>; -intel,processor-signature = <0x206a7>; -intel,checksum = <0xc9c91df0>; -intel,loader-revision = <1>; -intel,processor-flags = <0x12>; - /* The first 48-bytes are the public header which repeats the above data */ -data = < + 0x01000000 0x29000000 0x13201206 0xa7060200 0xf01dc9c9 0x01000000 0x12000000 0xd0270000 0x00280000 0x00000000 0x00000000 0x00000000 @@ -683,4 +687,3 @@ data = < 0x3b916d7c 0x5603319f 0x29007523 0xc9c7dc1c 0xd1f7212e 0x22ac1932 0x05c39a5a 0xd55081ce 0x589ae996 0xa998fcbe 0xd8df5512 0xef7d7a01 - >; diff --git a/arch/x86/dts/microcode/m12306a9_0000001b.dtsi b/arch/x86/dts/microcode/m12306a9_0000001b.dtsi index 53417c2..d4571dc 100644 --- a/arch/x86/dts/microcode/m12306a9_0000001b.dtsi +++ b/arch/x86/dts/microcode/m12306a9_0000001b.dtsi @@ -30,19 +30,23 @@ * --- * This is a device tree fragment. Use #include to add these properties to a * node. + * + * Date: Sat Sep 13 22:51:38 CST 2014 + * + * Device tree properties for this microcode: + * + * compatible = "intel,microcode"; + * intel,header-version = <1>; + * intel,update-revision = <0x1b>; + * intel,date-code = <0x5292014>; + * intel,processor-signature = <0x306a9>; + * intel,checksum = <0x579ae07a>; + * intel,loader-revision = <1>; + * intel,processor-flags = <0x12>; */ -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x1b>; -intel,date-code = <0x5292014>; -intel,processor-signature = <0x306a9>; -intel,checksum = <0x579ae07a>; -intel,loader-revision = <1>; -intel,processor-flags = <0x12>; - /* The first 48-bytes are the public header which repeats the above data */ -data = < + 0x01000000 0x1b000000 0x14202905 0xa9060300 0x7ae09a57 0x01000000 0x12000000 0xd02f0000 0x00300000 0x00000000 0x00000000 0x00000000 @@ -811,4 +815,3 @@ data = < 0xb8bfaaa9 0xa5914f75 0x77d26574 0xacfd459d 0x77f7cab2 0x249ebf26 0xef902bdd 0x77f6e48d 0x82497035 0x93333a9d 0x34ea9953 0x8f08d41c - >; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 4c9e265..5711510 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -193,7 +193,12 @@ microcode { update@0 { + compatible = "intel,microcode"; + intel,fsp-parser; + + data = < #include "microcode/m0130673322.dtsi" + >; }; }; -- 1.8.2.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot