Now that we have separate function to enable USB clocks, remove
enabling USB clocks from enable_basic_clocks(). Now board_usb_init()
should take care to invoke enable_usb_clocks() for enabling
USB clocks.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 12 ------------
arch/arm/cpu/armv7/omap5/hw_data.c | 30 ------------------------------
2 files changed, 42 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index cd8931e..30b4867 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -111,21 +111,9 @@ void enable_basic_clocks(void)
&cmper->emifclkctrl,
&cmper->otfaemifclkctrl,
&cmper->qspiclkctrl,
- &cmper->usb0clkctrl,
- &cmper->usbphyocp2scp0clkctrl,
- &cmper->usb1clkctrl,
- &cmper->usbphyocp2scp1clkctrl,
0
};
- setbits_le32(&cmper->usb0clkctrl,
- USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
- setbits_le32(&cmwkup->usbphy0clkctrl,
- USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
- setbits_le32(&cmper->usb1clkctrl,
- USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
- setbits_le32(&cmwkup->usbphy1clkctrl,
- USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
/* Select the Master osc clk as Timer2 clock source */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 1085bb3..19f2c43 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -460,13 +460,6 @@ void enable_basic_clocks(void)
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
- (*prcm)->cm_l3init_ocp2scp1_clkctrl,
- (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- (*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-#endif
-#endif
0
};
@@ -498,29 +491,6 @@ void enable_basic_clocks(void)
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
- /* Enable 960 MHz clock for dwc3 */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
- OPTFCLKEN_REFCLK960M);
-
- /* Enable 32 KHz clock for dwc3 */
- setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- /* Enable 960 MHz clock for dwc3 */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
- OPTFCLKEN_REFCLK960M);
-
- /* Enable 32 KHz clock for dwc3 */
- setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- /* Enable 60 MHz clock for USB2PHY2 */
- setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
- L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
-#endif
-#endif
-
/* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
--
1.7.9.5
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