Jagan,
On 13.08.2015 13:45, Jagan Teki wrote:
Please correct me if I'm wrong, but AFAIU this BAR thing
(CONFIG_SPI_FLASH_BAR) doesn't support to address e.g. a 64MiB SPI flash
contiguously. Only 16MiB areas. So for example its not possible to put
UBI/UBIFS in such a big partition.
Stefan,
No, BAR is accessing flash > 16MiB in 3-byte addressing mode, for your
example of
64MiB flash, it can grouped into 4 16MiB regions means 4 bank vales
bank0 to bank3
Based on the sf read/erase/write flash offsets, that particular bank
will enable an do
the relevant operations.
In-spite of having 4 byte addressing operations BAR should do exactly
same with existing
3-byte addressing.
Okay, thanks for the explanation. If this really is the case, and this
BAR support will seamlessly enable the access to the complete flash
area, then the 4-byte mode should really not be necessary.
I'm wondering though about 2 things:
a) Do all SPI NOR flash chips support this BAR mode?
b) If yes, why isn't BAR enabled per default?
c) Why doesn't the Linux kernel use this BAR mode?
Thanks,
Stefan
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
