From: Tang Yuantian <yuantian.t...@freescale.com>
Freescale ARM-based Layerscape LS2085A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2085aqds and ls2085ardb boards.
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
v2:
- rebase to the latest git tree
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 41 +++++++++++++++++++++++
arch/arm/include/asm/arch-fsl-lsch3/config.h | 20 +++++++++++
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 25 ++++++++++++++
arch/arm/include/asm/arch-fsl-lsch3/soc.h | 2 +-
board/freescale/ls2085aqds/ls2085aqds.c | 11 ++++++
board/freescale/ls2085ardb/ls2085ardb.c | 11 ++++++
6 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 2538001..0e6f07b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -11,6 +11,9 @@
#include <asm/arch-fsl-lsch3/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <ahci.h>
+#include <scsi.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -70,12 +73,50 @@ static void erratum_a009203(void)
#endif
}
+void ls2085a_sata_init(void)
+{
+ struct ccsr_ahci __iomem *ahci_base;
+
+ ahci_base = (void __iomem *)CONFIG_SYS_SATA2;
+ out_le32(&ahci_base->ppcfg, 0xa003fffe);
+
+ ahci_base = (void __iomem *)CONFIG_SYS_SATA1;
+ out_le32(&ahci_base->ppcfg, 0xa003fffe);
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int ls2085a_sata_start(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg;
+ int rc = -1;
+
+ cfg = in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ if ((cfg != 0x41) && (cfg != 0x42) && (cfg != 0x43) &&
+ (cfg != 0x44) && (cfg != 0x49) && (cfg != 0x4A)) {
+ printf("SATA disabled: serdes protocol doesn't support\n");
+ return rc;
+ }
+
+ rc = ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+ if (rc)
+ return rc;
+
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
erratum_a009203();
+ ls2085a_sata_init();
}
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index a4576dd..ba983f5 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -64,6 +64,26 @@
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x02210000)
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index d6bee60..a9a0447 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -180,4 +180,29 @@ struct ccsr_reset {
u32 ip_rev1; /* 0xbf8 */
u32 ip_rev2; /* 0xbfc */
};
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port phy4 config */
+ u32 pp5c; /* port phy5 config */
+ u32 paxic; /* port AXI config */
+ u32 axicc; /* AXI cache control */
+ u32 axipc; /* AXI PROT control */
+ u32 ptc; /* port Trans Config */
+ u32 pts; /* port Trans Status */
+ u32 plc; /* port link config */
+ u32 plc1; /* port link config1 */
+ u32 plc2; /* port link config2 */
+ u32 pls; /* port link status */
+ u32 pls1; /* port link status1 */
+ u32 pcmdc; /* port CMD config */
+ u32 ppcs; /* port phy control status */
+ u32 pberr; /* port 0/1 BIST error */
+ u32 cmds; /* port 0/1 CMD status error */
+};
#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
index 9a29272..5efc0ec 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -25,4 +25,4 @@ struct cpu_type {
void fsl_lsch3_early_init_f(void);
void cpu_name(char *name);
-
+int ls2085a_sata_start(void);
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c
b/board/freescale/ls2085aqds/ls2085aqds.c
index 08906a6..0d77904 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -249,6 +249,17 @@ int arch_misc_init(void)
}
#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ ls2085a_sata_start();
+#endif
+
+ return 0;
+}
+#endif
+
unsigned long get_dram_size_to_hide(void)
{
unsigned long dram_to_hide = 0;
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c
b/board/freescale/ls2085ardb/ls2085ardb.c
index 5e7997c..c354a22 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -217,6 +217,17 @@ int arch_misc_init(void)
}
#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ ls2085a_sata_start();
+#endif
+
+ return 0;
+}
+#endif
+
unsigned long get_dram_size_to_hide(void)
{
unsigned long dram_to_hide = 0;
--
2.1.0.27.g96db324
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