On Sat, Sep 12, 2015 at 09:36:54AM -0500, Scott Wood wrote: > On Sat, 2015-09-12 at 08:50 -0400, Tom Rini wrote: > > On Wed, Sep 02, 2015 at 02:29:12PM +0200, Stefan Roese wrote: > > > > > This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can > > > be used by boards equipped with a NAND chip that requires 4-bit ECC > > > strength. > > > The SPEAr600 HW ECC only supports 1-bit ECC strength. > > > > > > To enable SW BCH4, you need to specify this in your config header: > > > > > > #define CONFIG_NAND_ECC_BCH > > > #define CONFIG_BCH > > > > > > And use the command "nandecc bch4" to select this ECC scheme upon runtime. > > > > > > Tested on SPEAr600 x600 board. > > > > > > Signed-off-by: Stefan Roese <s...@denx.de> > > > Cc: Scott Wood <scottw...@freescale.com> > > > Acked-by: Viresh Kumar <viresh.ku...@linaro.org> > > > > Applied to u-boot/master, thanks! > > > > There's a v3, and some minor comments even on that one...
Mutter, sorry. Would you rather a revert of the series or just incremental on top? And aside, this is one reason I prefer resends of the whole series for anything non-trivial. 6 or 9 patches in patchwork is a lot clear that "oh, still in progress" as I clean things up rather than 1. -- Tom
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