On Thu, Oct 1, 2015 at 12:19 PM, Sinan Akman <si...@writeme.com> wrote: > I took a further look at this. I believe this won't work as readw > will now return the data in the wrong endianness. I think Wolfgang > also already pointed out at this. We would need to use the macro with > correct endianness for different platforms (ls1021atwr would need > big endian) and control this based on the watchdog endian setting in dts.
The imx platforms do not use dts in U-boot yet. > > However, there seems to be other problems here. The original > fix was intending to preserve the current set bits in wcr and > enable DTE. But in the case of ls1021atwr, the watcdog is not > initialized and out of reset we have SRS bit is set. This would > disable wdog_rst and prevent reset from working. Before the > fix it was actually the accidental setting of SRS to zero made > the reset working because a writew(WCR_WDE, &wdog->wcr) > would clear that bit, setting WDE alone would not generate wdog_rst. > > So I believe a proper fix would have the following steps : > - move watchdog driver to DM so that we can make use of endian type > - use macros with the endian type for accessing the registers > - enable hw_watchdog for the board so that it gets initialized to > a known value > - reset SRS to enable generation of wdog_rst, this will reset immediately > with 0x00 default WT value. > - or program the timeout and enable WDE so the board > resets after a longer timeout value if desired > > Does this make sense to everyone ? Looks good. 2015.10 release is only a few days away: do you think you could implement your proposal for the upcoming release? Regards, Fabio Estevam _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot