>From f22064087684b04d6d6ff105a4766a0902d361a8 Mon Sep 17 00:00:00 2001
From: Chin Liang See <cl...@altera.com>
Date: Thu, 15 Oct 2015 13:56:45 +0800
Subject: [PATCH 1/5] spi: cadence_qspi: Ensure spi_calibration is run
when
sclk change
Ensuring spi_calibration is run when there is a change of sclk
frequency. This will ensure the qspi flash access works for high
sclk frequency
Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Dinh Nguyen <dinh.li...@gmail.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Stefan Roese <s...@denx.de>
Cc: Vikas Manocha <vikas.mano...@st.com>
Cc: Jagannadh Teki <jt...@openedev.com>
Cc: Pavel Machek <pa...@denx.de>
Acked-by: Marek Vasut <ma...@denx.de>
Reviewed-by: Jagan Teki <jt...@openedev.com>
---
Changes for v4
- shift the checking for requested SCLK to the caller
Changes for v3
- no changes
Changes for v2
- remove frequency set before calibration
- introducing previous_hz to store requested frequency
- prevent calibration run when request same frequency
---
drivers/spi/cadence_qspi.c | 22 +++++++++++++---------
drivers/spi/cadence_qspi.h | 1 +
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46..c5a4276 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice
*bus, uint hz)
}
/* Calibration sequence to determine the read data capture delay
register */
-static int spi_calibration(struct udevice *bus)
+static int spi_calibration(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
u8 opcode_rdid = 0x9F;
@@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus)
}
/* use back the intended clock and find low range */
- cadence_spi_write_speed(bus, plat->max_hz);
+ cadence_spi_write_speed(bus, hz);
for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
/* Disable QSPI */
cadence_qspi_apb_controller_disable(base);
@@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus)
(range_hi + range_lo) / 2, range_lo, range_hi);
/* just to ensure we do once only when speed or chip select change */
- priv->qspi_calibrated_hz = plat->max_hz;
+ priv->qspi_calibrated_hz = hz;
priv->qspi_calibrated_cs = spi_chip_select(bus);
return 0;
@@ -126,14 +125,19 @@ static int cadence_spi_set_speed(struct udevice
*bus, uint hz)
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
- cadence_spi_write_speed(bus, hz);
-
- /* Calibration required for different SCLK speed or chip select */
- if (priv->qspi_calibrated_hz != plat->max_hz ||
+ /*
+ * Calibration required for different current SCLK speed, requested
+ * SCLK speed or chip select
+ */
+ if (priv->previous_hz != hz ||
+ priv->qspi_calibrated_hz != hz ||
priv->qspi_calibrated_cs != spi_chip_select(bus)) {
- err = spi_calibration(bus);
+ err = spi_calibration(bus, hz);
if (err)
return err;
+
+ /* prevent calibration run when same as previous request */
+ priv->previous_hz = hz;
}
/* Enable QSPI */
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 98e57aa..2912e36 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -38,6 +38,7 @@ struct cadence_spi_priv {
int qspi_is_init;
unsigned int qspi_calibrated_hz;
unsigned int qspi_calibrated_cs;
+ unsigned int previous_hz;
};
/* Functions call declaration */
--
2.2.0
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