When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".
Signed-off-by: York Sun <york...@freescale.com>
---
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 0d600db..df7ffb8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -192,6 +192,12 @@ int cpu_release(int nr, int argc, char * const argv[])
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
smp_kick_all_cpus(); /* only those with entry addr set will run */
+ /*
+ * When the first release command runs, all cores are set to go. Those
+ * without a valid entry address will be trapped by "wfe". "sev" kicks
+ * them off to check the address again. When set, they continue to run.
+ */
+ asm volatile("sev");
return 0;
}
--
1.7.9.5
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