From: Gong Qianyu <qianyu.g...@freescale.com>
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.
Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com>
---
V3:
- Remove the fixup for IFC.
V2:
- Modified rcw file to change core frequency to 1600MHz for SD_BOOT_QSPI.
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +++
arch/arm/dts/fsl-ls1043a-qds.dts | 14 +++++++++++++
arch/arm/dts/fsl-ls1043a.dtsi | 11 +++++++++++
board/freescale/ls1043aqds/MAINTAINERS | 1 +
.../ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg | 8 ++++++++
configs/ls1043aqds_sdcard_qspi_defconfig | 10 ++++++++++
include/configs/ls1043a_common.h | 13 ++++++++++++
include/configs/ls1043aqds.h | 23 ++++++++++++++++++++++
8 files changed, 83 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..4b1f792 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -219,6 +219,9 @@ void fsl_lsch2_early_init_f(void)
init_early_memctl_regs(); /* tighten IFC timing */
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
/* Make SEC reads and writes snoopable */
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP);
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts
index 93d73a6..9916f1b 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ b/arch/arm/dts/fsl-ls1043a-qds.dts
@@ -16,6 +16,7 @@
/ {
model = "LS1043A QDS Board";
aliases {
+ spi0 = &qspi;
spi1 = &dspi0;
};
};
@@ -49,6 +50,19 @@
};
};
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
&i2c0 {
status = "okay";
pca9547@77 {
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 85ea81e..f83cc3e 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,16 @@
interrupts = <0 55 0x4>;
clocks = <&clockgen 4 0>;
};
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1550000 0x10000>,
+ <0x40000000 0x4000000>;
+ num-cs = <2>;
+ big-endian;
+ status = "disabled";
+ };
};
};
diff --git a/board/freescale/ls1043aqds/MAINTAINERS
b/board/freescale/ls1043aqds/MAINTAINERS
index 0c7f648..868bb72 100644
--- a/board/freescale/ls1043aqds/MAINTAINERS
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -7,3 +7,4 @@ F: configs/ls1043aqds_defconfig
F: configs/ls1043aqds_nor_ddr3_defconfig
F: configs/ls1043aqds_nand_defconfig
F: configs/ls1043aqds_sdcard_ifc_defconfig
+F: configs/ls1043aqds_sdcard_qspi_defconfig
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
new file mode 100644
index 0000000..7783521
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
+00000000 00000000 00000000 00038800
+20124000 00001100 00000096 00000001
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig
b/configs/ls1043aqds_sdcard_qspi_defconfig
new file mode 100644
index 0000000..37e8b3c
--- /dev/null
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 38e5b9b..707405c 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -121,6 +121,7 @@
#endif
/* IFC */
+#ifndef CONFIG_SD_BOOT_QSPI
#define CONFIG_FSL_IFC
/*
* CONFIG_SYS_FLASH_BASE has the final address (core view)
@@ -139,6 +140,7 @@
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#endif
+#endif
/* I2C */
#define CONFIG_CMD_I2C
@@ -205,18 +207,29 @@
#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
#define CONFIG_SPI_FLASH_SST /* cs1 */
#define CONFIG_SPI_FLASH_EON /* cs2 */
+#ifndef CONFIG_SD_BOOT_QSPI
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_CS 0
#endif
+#endif
/* FMan ucode */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 43107b0..cb519e1 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -85,8 +85,12 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW
board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
+#else
#define CONFIG_SYS_FSL_PBL_RCW
board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
#endif
+#endif
/* SATA */
#define CONFIG_LIBATA
@@ -108,6 +112,7 @@ unsigned long get_board_ddr_clk(void);
/*
* IFC Definitions
*/
+#ifndef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
@@ -191,6 +196,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#endif
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
@@ -198,6 +204,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
#endif
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
/*
* QIXIS Definitions
*/
@@ -214,6 +226,7 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_SD_QSPI 0xff
#define QIXIS_RCW_SRC_NAND 0x106
#define QIXIS_RCW_SRC_SD 0x040
#define QIXIS_RST_CTL_RESET 0x41
@@ -342,6 +355,16 @@ unsigned long get_board_ddr_clk(void);
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
+/* QSPI device */
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+#endif
+
/*
* Miscellaneous configurable options
*/
--
2.1.0.27.g96db324
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