On 01/09/2016 03:07 AM, Stefan Roese wrote:
> @@ -100,14 +100,24 @@
>   #if defined(CONFIG_ARMADA_38X)
>   /* SAR values for Armada 38x */
>   #define CONFIG_SAR_REG              (MVEBU_REGISTER(0x18600))
> +
>   #define SAR_CPU_FREQ_OFFS   10
>   #define SAR_CPU_FREQ_MASK   (0x1f << SAR_CPU_FREQ_OFFS)
>   #define SAR_BOOT_DEVICE_OFFS        4
>   #define SAR_BOOT_DEVICE_MASK        (0x1f << SAR_BOOT_DEVICE_OFFS)
> +
> +#define BOOT_DEV_SEL_OFFS    4
> +#define BOOT_DEV_SEL_MASK    (0x1f << BOOT_DEV_SEL_OFFS)
> +
It is a little confusing that this is added incorrectly here, then 
corrected in the next patch ... could this just be added as 0x3f here?

> +#define BOOT_FROM_UART               0x28
> +#define BOOT_FROM_SPI                0x32
> +#define BOOT_FROM_MMC                0x30
> +#define BOOT_FROM_MMC_ALT    0x31
>
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