This graphics init code is best placed in the gma init code. Move the code
and drop the function.
Signed-off-by: Simon Glass <s...@chromium.org>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 1 -
arch/x86/cpu/ivybridge/gma.c | 4 ++++
arch/x86/cpu/ivybridge/lpc.c | 7 -------
arch/x86/include/asm/arch-ivybridge/pch.h | 1 -
4 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 188b7da..9e7e30a 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -29,7 +29,6 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
hose = pci_bus_to_hose(0);
- lpc_enable(PCH_LPC_DEV);
lpc_init_extra(hose, PCH_LPC_DEV);
/* Cause the SATA device to do its init */
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 1748f7f..b94536c 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -806,6 +806,10 @@ int gma_func0_init(struct udevice *dev, const void *blob,
int node)
u32 reg32;
int ret;
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+
ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
if (!nbridge)
return -ENODEV;
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 0d85de2..44c4825 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -602,13 +602,6 @@ int lpc_init_extra(struct pci_controller *hose, pci_dev_t
dev)
return 0;
}
-void lpc_enable(pci_dev_t dev)
-{
- /* Enable PCH Display Port */
- writew(0x0010, RCB_REG(DISPBDF));
- setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
-}
-
static int bd82x6x_lpc_early_init(struct udevice *dev)
{
/* Setting up Southbridge. In the northbridge code. */
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h
b/arch/x86/include/asm/arch-ivybridge/pch.h
index f35803b..682a557 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -471,6 +471,5 @@ void pch_iobp_update(u32 address, u32 andvalue, u32
orvalue);
#define TCO2_STS 0x66
int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev);
-void lpc_enable(pci_dev_t dev);
#endif
--
2.6.0.rc2.230.g3dd15c0
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