Dear Scott Wood, In message <20090818151213.gb26...@b07421-ec1.am.freescale.net> you wrote: > On Tue, Aug 18, 2009 at 08:56:03AM -0500, Paulraj, Sandeep wrote: > > > > + case NAND_ECC_READSYN: > > > > + val = emif_regs->NAND4BITECC1; > > > > > > Use I/O accessors. > > I could not understand this one. It is done similarly > > nand_davinci_enable_hwecc which is used for 1 BIT ECC. > > NANDFCR is a control register and we have to write the appropriate valvue > > to it. > > We similarly write to other register that are part of the IP in other > > sections of this driver. > > Well, the comment applies to the rest of the driver too. I won't NACK > because of it, but it's something to consider in the future.
Well, I will NAK it, then. We should really write clean code these days. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Some people march to the beat of a different drummer. And some people tango! _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
