Hi Andreas, > -----Original Message----- > From: Andreas Bießmann [mailto:andreas.de...@googlemail.com] > Sent: 2016年2月2日 16:23 > To: Yang, Wenyou <wenyou.y...@atmel.com>; U-Boot Mailing List <u- > b...@lists.denx.de> > Cc: Heiko Schocher <h...@denx.de>; andreas.de...@googlemail.com > Subject: Re: [RESEND PATCH v3 2/5] ARM: at91: clock: add a new file to handle > clock > > Hi Wenyou, > > On 02.02.2016 03:31, Wenyou Yang wrote: > > To reduce the duplicated code, add a new file to accommodate the > > peripheral's and system's clock handle code, shared with the SoCs with > > different ARM core. > > > > Signed-off-by: Wenyou Yang <wenyou.y...@atmel.com> > > Tested-by: Heiko Schocher <h...@denx.de> > > --- > > > > Changes in v3: > > - fix incorrectly used the indicator '&' to achieve the variable > > pointer of pmc->pcer and pmc->pcdr. > > > > Changes in v2: None > > > > arch/arm/mach-at91/Makefile | 1 + > > arch/arm/mach-at91/arm926ejs/clock.c | 7 ---- > > arch/arm/mach-at91/armv7/clock.c | 26 ------------ > > arch/arm/mach-at91/clock.c | 72 > +++++++++++++++++++++++++++++++++ > > arch/arm/mach-at91/include/mach/clk.h | 2 + > > 5 files changed, 75 insertions(+), 33 deletions(-) create mode > > 100644 arch/arm/mach-at91/clock.c > > > > diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile > > index 5b89617..d071072 100644 > > --- a/arch/arm/mach-at91/Makefile > > +++ b/arch/arm/mach-at91/Makefile > > @@ -14,6 +14,7 @@ obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o > > matrix.o atmel_sfr.o obj-y += spl.o endif > > > > +obj-y += clock.o > > obj-$(CONFIG_CPU_ARM920T) += arm920t/ > > obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/ > > obj-$(CONFIG_CPU_V7) += armv7/ > > diff --git a/arch/arm/mach-at91/arm926ejs/clock.c > > b/arch/arm/mach-at91/arm926ejs/clock.c > > index 8d6934e..c8b5e10 100644 > > --- a/arch/arm/mach-at91/arm926ejs/clock.c > > +++ b/arch/arm/mach-at91/arm926ejs/clock.c > > @@ -242,10 +242,3 @@ void at91_mck_init(u32 mckr) > > while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) > > ; > > } > > - > > -void at91_periph_clk_enable(int id) > > -{ > > - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > - > > - writel(1 << id, &pmc->pcer); > > -} > > diff --git a/arch/arm/mach-at91/armv7/clock.c > > b/arch/arm/mach-at91/armv7/clock.c > > index 41dbf16..81e9f69 100644 > > --- a/arch/arm/mach-at91/armv7/clock.c > > +++ b/arch/arm/mach-at91/armv7/clock.c > > @@ -150,32 +150,6 @@ void at91_mck_init(u32 mckr) > > ; > > } > > > > -void at91_periph_clk_enable(int id) > > -{ > > - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > - u32 regval; > > - > > - if (id > AT91_PMC_PCR_PID_MASK) > > - return; > > - > > - regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id; > > - > > - writel(regval, &pmc->pcr); > > -} > > - > > -void at91_periph_clk_disable(int id) > > -{ > > - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > - u32 regval; > > - > > - if (id > AT91_PMC_PCR_PID_MASK) > > - return; > > - > > - regval = AT91_PMC_PCR_CMD_WRITE | id; > > - > > - writel(regval, &pmc->pcr); > > -} > > - > > int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) > > { > > struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git > > a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c new file > > mode 100644 index 0000000..d1c4b76 > > --- /dev/null > > +++ b/arch/arm/mach-at91/clock.c > > @@ -0,0 +1,72 @@ > > +/* > > + * Copyright (C) 2015 Atmel Corporation > > + * Wenyou Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <asm/io.h> > > +#include <asm/arch/hardware.h> > > +#include <asm/arch/at91_pmc.h> > > + > > +void at91_periph_clk_enable(int id) > > +{ > > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > + > > +#ifdef CPU_HAS_PCR > > + u32 regval; > > + u32 div_value; > > + > > + if (id > AT91_PMC_PCR_PID_MASK) > > + return; > > + > > + writel(id, &pmc->pcr); > > + > > + div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV; > > + > > + regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | > div_value; > > + > > + writel(regval, &pmc->pcr); > > +#else > > + u32 mask = 0x01 << (id % 32); > > + void *addr = (id / 32) ? &pmc->pcer1 : &pmc->pcer; > > Could you please address my question to the last sent version? > > ---8<--- > Isn't the pmc->pcer1 only available on devices which have CPU_HAS_PCR? > The old behaviour would be to just access unconditionally the pmc->pcer here. > Could you please elaborate?
Yes, you are right. PCR is introduced from AT91SAM9X5. I will be careful. Thank you. > --->8--- > > Andreas > > > + > > + writel(mask, addr); > > +#endif > > +} > > + > > +void at91_periph_clk_disable(int id) > > +{ > > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > + > > +#ifdef CPU_HAS_PCR > > + u32 regval; > > + > > + if (id > AT91_PMC_PCR_PID_MASK) > > + return; > > + > > + regval = AT91_PMC_PCR_CMD_WRITE | id; > > + > > + writel(regval, &pmc->pcr); > > +#else > > + u32 mask = 0x01 << (id % 32); > > + void *addr = (id / 32) ? &pmc->pcdr1 : &pmc->pcdr; > > + > > + writel(mask, addr); > > +#endif > > +} > > + > > +void at91_system_clk_enable(int sys_clk) { > > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > + > > + writel(sys_clk, &pmc->scer); > > +} > > + > > +void at91_system_clk_disable(int sys_clk) { > > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > > + > > + writel(sys_clk, &pmc->scdr); > > +} > > diff --git a/arch/arm/mach-at91/include/mach/clk.h > > b/arch/arm/mach-at91/include/mach/clk.h > > index ad83927..bef4e1c 100644 > > --- a/arch/arm/mach-at91/include/mach/clk.h > > +++ b/arch/arm/mach-at91/include/mach/clk.h > > @@ -128,5 +128,7 @@ void at91_periph_clk_enable(int id); void > > at91_periph_clk_disable(int id); int > > at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div); > > u32 at91_get_periph_generated_clk(u32 id); > > +void at91_system_clk_enable(int sys_clk); void > > +at91_system_clk_disable(int sys_clk); > > > > #endif /* __ASM_ARM_ARCH_CLK_H__ */ > > Best Regards, Wenyou Yang _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot