* Added a generic function fsl_pci_init_port in drivers/pci/fsl_pci.c
to initialize a PCIe port.
* fsl_pci_init_port can be called from board specific pcie initialization
routine, per-port.
* This will reduce the code redundancy in the most of the Freescale board
specific PCIe inits.
* All the FSL 85xx boards can use it for PCIe initialization.
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
- next patch following it makes use of this patch for PCIe initialization
on P1&P2 RDB
drivers/pci/fsl_pci_init.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/fsl_pci.h | 26 ++++++++++++++++++++++++++
2 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index ee89aaa..9e9e1b7 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -412,6 +412,47 @@ void fsl_pci_init(struct pci_controller *hose, u32
cfg_addr, u32 cfg_data)
}
}
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+ struct pci_controller *hose, int busno)
+{
+ volatile ccsr_fsl_pci_t *pci;
+ struct pci_region *r;
+
+ pci = (ccsr_fsl_pci_t *) pci_info->regs;
+
+ if (in_be32(&pci->pme_msg_det)) {
+ out_be32(&pci->pme_msg_det, 0xffffffff);
+ debug (" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+
+ r = hose->regions + hose->region_count;
+
+ /* outbound memory */
+ pci_set_region(r++,
+ pci_info->mem_bus,
+ pci_info->mem_phys,
+ pci_info->mem_size,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ pci_info->io_bus,
+ pci_info->io_phys,
+ pci_info->io_size,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+ hose->first_busno = busno;
+
+ fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+
+ printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
+ hose->first_busno, hose->last_busno);
+
+ return(hose->last_busno + 1);
+}
+
/* Enable inbound PCI config cycles for agent/endpoint interface */
void fsl_pci_config_unlock(struct pci_controller *hose)
{
diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index b2ff0e9..2b6421a 100644
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -154,4 +154,30 @@ typedef struct ccsr_pci {
char res24[252];
} ccsr_fsl_pci_t;
+struct fsl_pci_info {
+ phys_size_t regs;
+ pci_addr_t mem_bus;
+ phys_size_t mem_phys;
+ pci_size_t mem_size;
+ pci_addr_t io_bus;
+ phys_size_t io_phys;
+ pci_size_t io_size;
+ int pci_num;
+};
+
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+ struct pci_controller *hose, int busno);
+
+#define SET_STD_PCIE_INFO(x, num) \
+{ \
+ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
+ x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
+ x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
+ x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
+ x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
+ x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
+ x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+ x.pci_num = num; \
+}
+
#endif
--
1.5.6.5
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