On 02/25/2016 05:49 PM, Alexander Graf wrote:
Howdy,
Currently on arm64 there is a big pile of mess when it comes to MMU
support and page tables. Each board does its own little thing and the
generic code is pretty dumb and nobody actually uses it.
This patch set tries to clean that up. After this series is applied,
all boards except for the FSL Layerscape ones are converted to the
new generic page table logic and have icache+dcache enabled.
The new code always uses 4k page size. It dynamically allocates 1G or
2M pages for ranges that fit. When a dcache attribute request comes in
that requires a smaller granularity than our previous allocation could
fulfill, pages get automatically split.
I have tested and verified the code works on HiKey (bare metal),
vexpress64 (Foundation Model) and zynqmp (QEMU). The TX1 target is
untested, but given the simplicity of the maps I doubt it'll break.
ThunderX in theory should also work, but I haven't tested it. I would
be very happy if people with access to those system could give the patch
set a try.
With this we're a big step closer to a good base line for EFI payload
support, since we can now just require that all boards always have dcache
enabled.
I would also be incredibly happy if some Freescale people could look
at their MMU code and try to unify it into the now cleaned up generic
code. I don't think we're far off here.
Tested-by: Stephen Warren <swar...@nvidia.com>
(On p2371-0000 and p2371-2180)
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