The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.
Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <mschif...@universe-factory.net>
Cc: Paul Burton <paul.bur...@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
---
Hi,
I've noticed this when reading the code to understand how the cache
instruction is used. I'm not sure if this bug had any practical
consequences, or if nowadays all relevant compilers have
__builtin_mips_cache anyways.
Please keep me in Cc in follow-up mails, I'm not subscribed to the u-boot
ML.
Matthias
arch/mips/include/asm/cacheops.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index a3b07c6..002b839 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -16,7 +16,7 @@ static inline void mips_cache(int op, const volatile void
*addr)
#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
__builtin_mips_cache(op, addr);
#else
- __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
+ __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
#endif
}
--
2.7.2
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