On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
Both devices can be enabled at the same time.
Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
arch/arm/dts/uniphier-ph1-sld3-ref.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index c4601cf..099df83 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -57,6 +57,10 @@
status = "okay";
};
+&emmc {
+ status = "okay";
+};
+
&sd {
status = "okay";
};
--
1.9.1
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