To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

Signed-off-by: Mario Six <mario....@gdsys.cc>
Cc: York Sun <york....@nxp.com>
Cc: Simon Glass <s...@chromium.org>
---
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 235a635..e6e1688 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
        u32 mas0, mas1, mas2, mas3, mas7;
-       int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
        /* Pointer is writable since we allocated a register for it */
        gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

-       /*
-        * Clear initial global data
-        *   we don't use memset so we can share this code with NAND_SPL
-        */
-       for (i = 0; i < sizeof(gd_t); i++)
-               ((char *)gd)[i] = 0;
-
 #ifdef CONFIG_QEMU_E500
        /*
         * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d867e2a..e6b5203 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1152,6 +1152,34 @@ _start_cont:
        /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
        lis     r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
        ori     r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+       /* Leave 16+ byte for back chain termination and NULL return address */
+       subi    r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+       /* End of RAM */
+       lis     r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+       ori     r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+       li      r0,0
+
+1:     subi    r4,r4,4
+       stw     r0,0(r4)
+       cmplw   r4,r3
+       bne     1b
+
+       lis     r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+       ori     r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+       addi    r3,r3,16        /* Pre-relocation malloc area */
+       stw     r3,GD_MALLOC_BASE(r4)
+       subi    r3,r3,16
+
+       /* Fix issue with exception handler alignment */
+       nop
+       nop
+       nop
+#endif
        li      r0,0
        stw     r0,0(r3)        /* Terminate Back Chain */
        stw     r0,+4(r3)       /* NULL return address. */
--
2.7.0.GIT

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