On Wed, Apr 20, 2016 at 03:46:50PM -0600, Stephen Warren wrote: > From: Stephen Warren <swar...@nvidia.com> > > Tegra20's PCIe controller has a couple of quirks. There are workarounds in > the driver for these, but they don't work after the DM conversion: > > 1) The PCI_CLASS value is wrong in HW. > > This is worked around in pci_tegra_read_config() by patching up the value > read from that register. Pre-DM, the PCIe core always read this via a > 16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used, > so we need to check for offset 0x8 instead. Mask the offset value back to > 32-bit alignment to make this work in all cases. > > 2) Accessing devices other than dev 1 causes a data abort. > > Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code > called during enumeration while iterating over a bus. The DM PCIe core > doesn't use this function. Instead, enhance tegra_pcie_conf_address() to > validate the bdf being accessed, and refuse to access invalid devices. > Since pci_skip_dev() isn't used, delete it. > > I've also validated that both these WARs are only needed for Tegra20, by > testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in > conditionally. > > Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model > for PCI") > Signed-off-by: Stephen Warren <swar...@nvidia.com> > --- > drivers/pci/pci_tegra.c | 21 ++++++++++----------- > 1 file changed, 10 insertions(+), 11 deletions(-)
Neat: Reviewed-by: Thierry Reding <tred...@nvidia.com>
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