As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit
70e21b06425ad6e1e90931333a704a600941cfff, the workaround to flush dcache
is unnecessary and will be removed.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..9a5a6b5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -396,9 +396,6 @@ static inline void final_mmu_setup(void)
flush_dcache_range((ulong)level0_table,
(ulong)level0_table + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_DPAA_FMAN
- flush_dcache_all();
-#endif
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
MEMORY_ATTRIBUTES);
--
2.1.0.27.g96db324
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