Signed-off-by: Martha M Stan <mm...@silicontkx.com> --- board/davedenx/aria/aria.c | 2 +- board/esd/mecp5123/mecp5123.c | 2 +- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- cpu/mpc512x/fixed_sdram.c | 94 ++++++++++++++++++++----------- include/asm-ppc/immap_512x.h | 5 +- include/asm-ppc/mpc512x.h | 2 +- include/configs/aria.h | 6 +-- include/configs/mecp5123.h | 5 +- include/configs/mpc5121ads.h | 6 +-- 9 files changed, 72 insertions(+), 52 deletions(-)
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index 2064aa2..cc69c9d 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -101,7 +101,7 @@ int board_early_init_f(void) phys_size_t initdram (int board_type) { - return fixed_sdram(); + return fixed_sdram(NULL, NULL, 0); } int misc_init_r(void) diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index f591e32..5139358 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -135,7 +135,7 @@ int board_early_init_f(void) phys_size_t initdram(int board_type) { - return get_ram_size(0, fixed_sdram()); + return get_ram_size(0, fixed_sdram(NULL, NULL, 0)); } int misc_init_r(void) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index a0d7a82..8defb00 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -137,7 +137,7 @@ phys_size_t initdram(int board_type) { u32 msize = 0; - msize = fixed_sdram(); + msize = fixed_sdram(NULL, NULL, 0); return msize; } diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index d906903..eb0811c 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -20,23 +20,73 @@ * MA 02111-1307 USA * */ - +#define DEBUG 0xff #include <common.h> #include <asm/io.h> #include <asm/mpc512x.h> +/* config settings in order of the 4 mddrc cfg registers */ +u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, + CONFIG_SYS_MDDRC_TIME_CFG0, + CONFIG_SYS_MDDRC_TIME_CFG1, + CONFIG_SYS_MDDRC_TIME_CFG2 +}; + +u32 default_init_sequence[] = { + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_EM2, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_EM2, + CONFIG_SYS_MICRON_EM3, + CONFIG_SYS_MICRON_EN_DLL, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_MICRON_OCD_DEFAULT, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_NOP +}; + /* * fixed sdram init: * The board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ -long int fixed_sdram(void) +long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_sequence, int seq_table_size) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); u32 i; + /* take default settings and init sequence if necessary */ + if (mddrc_config == 0) + mddrc_config = default_mddrc_config; + if (dram_init_sequence == 0) { + dram_init_sequence = default_init_sequence; + seq_table_size = sizeof(default_init_sequence)/sizeof(u32); + } + /* Initialize IO Control */ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); @@ -46,7 +96,7 @@ long int fixed_sdram(void) sync_law(&im->sysconf.ddrlaw.ar); /* Enable DDR */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -74,40 +124,18 @@ long int fixed_sdram(void) out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); /* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[0]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[1] & MDDRC_TIME_CFG0_RFRSH0); + out_be32(&im->mddrc.ddr_time_config1, mddrc_config[2]); + out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); /* Initialize DDR */ - for (i = 0; i < 10; i++) - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + for (i = 0; i < seq_table_size; i++) + out_be32(&im->mddrc.ddr_command, dram_init_sequence[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[1]); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[0] & MDDRC_SYS_CFG_RUN); return msize; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 24e6c69..13d3d0e 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -45,7 +45,6 @@ #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) - #ifndef __ASSEMBLY__ typedef struct law512x { u32 bar; /* Base Addr Register */ @@ -341,6 +340,10 @@ typedef struct ddr512x { u32 res2[0x3AD]; } ddr512x_t; +/* MDDRC SYS CFG and Timing CFG0 Registers */ +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_RUN ~(0x01 << 28) +#define MDDRC_TIME_CFG0_RFRSH0 0x0000FFFF /* * DMA/Messaging Unit diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h index 20456f5..6a65492 100644 --- a/include/asm-ppc/mpc512x.h +++ b/include/asm-ppc/mpc512x.h @@ -50,7 +50,7 @@ static inline void sync_law(volatile void *addr) /* * Prototypes */ -extern long int fixed_sdram(void); +extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_sequence, int seq_table_size); extern int mpc5121_diu_init(void); extern void ide_set_reset(int idereset); diff --git a/include/configs/aria.h b/include/configs/aria.h index 4211113..a6fa168 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -143,14 +143,10 @@ (0 << 0) /* FIFO_UV_EN */ \ ) -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28)) +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1ecae00..8bed9d1 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -112,12 +112,9 @@ * [04:00] DRAM tRPA */ #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174d..d96e7f5 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -132,18 +132,14 @@ */ #ifdef CONFIG_MPC5121ADS_REV2 #define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 #else #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -- 1.5.2.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot