Hi.
2016-06-30 17:51 GMT+09:00 Gong Qianyu <qianyu.g...@nxp.com>: > From: Mingkai Hu <mingkai...@nxp.com> > > Data coherency is enabled only when the CPUECTLR.SMPEN bit is > set. The SMPEN bit should be set before enabling the data cache. > If not enabled, the cache is not coherent with other cores and > data corruption could occur. > > Signed-off-by: Mingkai Hu <mingkai...@nxp.com> > Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com> > > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S > index 670e323..735dd67 100644 > --- a/arch/arm/cpu/armv8/start.S > +++ b/arch/arm/cpu/armv8/start.S > @@ -81,6 +81,11 @@ reset: > msr cpacr_el1, x0 /* Enable FP/SIMD */ > 0: > > + /* Enalbe SMPEN bit */ > + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ > + orr x0, x0, #0x40 > + msr S3_1_c15_c2_1, x0 > + > /* Apply ARM core specific erratas */ > bl apply_core_errata > I guess this code is necessary in U-Boot if we want to boot the system without ARM Trusted Firmware. I can see equivalent code only in arch/arm/mach-uniphier/arm64/smp.S (my SoC) So, I guess all of the other SoCs use ATF and setup this register there. One more thing, I could find the description about this register only in each Cortex-A* TRM, but not in v8 ARM ARM. However, I assume this register exists in all of ARMv8 variants. (but I am not 100% sure because I am not an expert in this area.) Otherwise, this patch looks good to me (and if it is accepted, I can remove equivalent code from my local file) Reviewed-by: Masahiro Yamada <yamada.masah...@socionext.com> -- Best Regards Masahiro Yamada _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot