On 2016-07-19 07:14, Stefano Babic wrote:
> Hi Stefan,
>
>
> just a couple of minor things:
>
>
> On 13/07/2016 09:25, Stefan Agner wrote:
>> From: Stefan Agner <stefan.ag...@toradex.com>
>>
>> This commit adds support for the Toradex Computer on Modules
>> Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
>> can be easily supported by one board. The board code detects RAM
>> size at runtime which is one of the differences between the two
>> boards. The board also uses the UART's in DTE mode, hence making
>> use of the new DTE support via serial DM.
>>
>> Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
>> ---
>>
>> arch/arm/cpu/armv7/mx7/Kconfig | 7 +
>> board/toradex/colibri_imx7/Kconfig | 12 +
>> board/toradex/colibri_imx7/MAINTAINERS | 6 +
>> board/toradex/colibri_imx7/Makefile | 6 +
>> board/toradex/colibri_imx7/colibri_imx7.c | 420
>> ++++++++++++++++++++++++++++++
>> board/toradex/colibri_imx7/imximage.cfg | 150 +++++++++++
>> configs/colibri_imx7_defconfig | 40 +++
>> include/configs/colibri_imx7.h | 248 ++++++++++++++++++
>> 8 files changed, 889 insertions(+)
>> create mode 100644 board/toradex/colibri_imx7/Kconfig
>> create mode 100644 board/toradex/colibri_imx7/MAINTAINERS
>> create mode 100644 board/toradex/colibri_imx7/Makefile
>> create mode 100644 board/toradex/colibri_imx7/colibri_imx7.c
>> create mode 100644 board/toradex/colibri_imx7/imximage.cfg
>> create mode 100644 configs/colibri_imx7_defconfig
>> create mode 100644 include/configs/colibri_imx7.h
>>
>> diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
>> index dd51384..5fdc8dd 100644
>> --- a/arch/arm/cpu/armv7/mx7/Kconfig
>> +++ b/arch/arm/cpu/armv7/mx7/Kconfig
>> @@ -27,12 +27,19 @@ config TARGET_WARP7
>> select DM
>> select DM_THERMAL
>>
>> +config TARGET_COLIBRI_IMX7
>> + bool "Support Colibri iMX7S/iMX7D modules"
>> + select DM
>> + select DM_SERIAL
>> + select DM_THERMAL
>> +
>> endchoice
>>
>> config SYS_SOC
>> default "mx7"
>>
>> source "board/freescale/mx7dsabresd/Kconfig"
>> +source "board/toradex/colibri_imx7/Kconfig"
>> source "board/warp7/Kconfig"
>>
>> endif
>> diff --git a/board/toradex/colibri_imx7/Kconfig
>> b/board/toradex/colibri_imx7/Kconfig
>> new file mode 100644
>> index 0000000..622ce66
>> --- /dev/null
>> +++ b/board/toradex/colibri_imx7/Kconfig
>> @@ -0,0 +1,12 @@
>> +if TARGET_COLIBRI_IMX7
>> +
>> +config SYS_BOARD
>> + default "colibri_imx7"
>> +
>> +config SYS_VENDOR
>> + default "toradex"
>> +
>> +config SYS_CONFIG_NAME
>> + default "colibri_imx7"
>> +
>> +endif
>> diff --git a/board/toradex/colibri_imx7/MAINTAINERS
>> b/board/toradex/colibri_imx7/MAINTAINERS
>> new file mode 100644
>> index 0000000..5ffb241
>> --- /dev/null
>> +++ b/board/toradex/colibri_imx7/MAINTAINERS
>> @@ -0,0 +1,6 @@
>> +Colibri iMX7
>> +M: Stefan Agner <stefan.ag...@toradex.com>
>> +S: Maintained
>> +F: board/toradex/colibri_imx7/
>> +F: include/configs/colibri_imx7.h
>> +F: configs/colibri_imx7_defconfig
>
> I wonder we never add imximage.cfg into the MAINTAINERS. Boards with SPL
> have a central and empty imximage.cfg, for the other ones we should add
> it to the list. (Note: I have currently seen that no board having its
> own imximage.cfg does not list it in the MAINTAINERS file).
>
I added the directory where imximage.cfg is located in
(board/toradex/colibri_imx7/). We also don't add other files in there, I
think the scripts work fine with directories specified without
specifying the individual files...
>> diff --git a/board/toradex/colibri_imx7/Makefile
>> b/board/toradex/colibri_imx7/Makefile
>> new file mode 100644
>> index 0000000..ea597de
>> --- /dev/null
>> +++ b/board/toradex/colibri_imx7/Makefile
>> @@ -0,0 +1,6 @@
>> +# Copyright (C) 2016 Toradex AG
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y := colibri_imx7.o
>> diff --git a/board/toradex/colibri_imx7/colibri_imx7.c
>> b/board/toradex/colibri_imx7/colibri_imx7.c
>> new file mode 100644
>> index 0000000..b36f580
>> --- /dev/null
>> +++ b/board/toradex/colibri_imx7/colibri_imx7.c
>> @@ -0,0 +1,420 @@
>> +/*
>> + * Copyright (C) 2016 Toradex AG
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/arch/mx7-pins.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <asm/gpio.h>
>> +#include <asm/imx-common/boot_mode.h>
>> +#include <asm/imx-common/iomux-v3.h>
>> +#include <asm/imx-common/mxc_i2c.h>
>> +#include <asm/io.h>
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <dm/platform_data/serial_mxc.h>
>> +#include <fsl_esdhc.h>
>> +#include <i2c.h>
>> +#include <linux/sizes.h>
>> +#include <mmc.h>
>> +#include <miiphy.h>
>> +#include <netdev.h>
>> +#include <usb/ehci-ci.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
>> + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
>> +
>> +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
>> + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
>> +
>> +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
>> +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
>> +
>> +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
>> +
>> +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
>> + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
>> +
>> +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
>> + PAD_CTL_DSE_3P3V_49OHM)
>> +
>> +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW |
>> PAD_CTL_HYS)
>> +
>> +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
>> +
>> +#ifdef CONFIG_SYS_I2C_MXC
>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>> +/* I2C1 for PMIC */
>> +static struct i2c_pads_info i2c_pad_info1 = {
>> + .scl = {
>> + .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
>> + .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
>> + .gp = IMX_GPIO_NR(1, 4),
>> + },
>> + .sda = {
>> + .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
>> + .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
>> + .gp = IMX_GPIO_NR(1, 5),
>> + },
>> +};
>> +/* I2C4 for Colibri I2C */
>> +static struct i2c_pads_info i2c_pad_info4 = {
>> + .scl = {
>> + .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
>> + .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
>> + .gp = IMX_GPIO_NR(7, 8),
>> + },
>> + .sda = {
>> + .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
>> + .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
>> + .gp = IMX_GPIO_NR(7, 9),
>> + },
>> +};
>> +#endif
>> +
>> +int dram_init(void)
>> +{
>> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
>> +
>> + return 0;
>> +}
>> +
>> +static iomux_v3_cfg_t const uart1_pads[] = {
>> + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const usdhc1_pads[] = {
>> + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +
>> + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +#ifdef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const gpmi_pads[] = {
>> + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B |
>> MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
>> +};
>> +
>> +static void setup_gpmi_nand(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
>> +
>> + /* NAND_USDHC_BUS_CLK is set in rom */
>> + set_clk_nand();
>> +}
>> +#endif
>> +
>> +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
>> + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +
>> + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +
>> +#ifdef CONFIG_VIDEO_MXS
>> +static iomux_v3_cfg_t const lcd_pads[] = {
>> + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const backlight_pads[] = {
>> + /* Backlight On */
>> + MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> + /* Backlight PWM<A> (multiplexed pin) */
>> + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
>> +#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
>> +
>> +static int setup_lcd(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
>> +
>> + imx_iomux_v3_setup_multiple_pads(backlight_pads,
>> ARRAY_SIZE(backlight_pads));
>> +
>> + /* Set BL_ON */
>> + gpio_request(GPIO_BL_ON, "BL_ON");
>> + gpio_direction_output(GPIO_BL_ON, 1);
>> +
>> + /* Set PWM<A> to full brightness (assuming inversed polarity) */
>> + gpio_request(GPIO_PWM_A, "PWM<A>");
>> + gpio_direction_output(GPIO_PWM_A, 0);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_FEC_MXC
>> +static iomux_v3_cfg_t const fec1_pads[] = {
>> +#ifndef CONFIG_COLIBRI_EXT_PHYCLK
>
> This is a new CONFIG_, undocumented. We have really the setup for other
> boards, too. Anyway, moved to Kconfig ?
>
Ok, will do.
>> + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) |
>> MUX_MODE_SION,
>> +#else
>> + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +#endif
>> + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
>> + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
>> + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 |
>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 |
>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_fec(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
>> +}
>> +#endif
>> +
>> +static void setup_iomux_uart(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>> +}
>> +
>> +#ifdef CONFIG_FSL_ESDHC
>> +
>> +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
>> +
>> +static struct fsl_esdhc_cfg usdhc_cfg[] = {
>> + {USDHC1_BASE_ADDR, 0, 4},
>> +};
>> +
>> +int board_mmc_getcd(struct mmc *mmc)
>> +{
>> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>> + int ret = 0;
>> +
>> + switch (cfg->esdhc_base) {
>> + case USDHC1_BASE_ADDR:
>> + ret = !gpio_get_value(USDHC1_CD_GPIO);
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + int i, ret;
>> + /* USDHC1 is mmc0 */
>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>> + switch (i) {
>> + case 0:
>> + imx_iomux_v3_setup_multiple_pads(
>> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
>> + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
>> + gpio_direction_input(USDHC1_CD_GPIO);
>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> + break;
>> + default:
>> + printf("Warning: you configured more USDHC controllers"
>> + "(%d) than supported by the board\n", i + 1);
>> + return -EINVAL;
>> + }
>> +
>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_FEC_MXC
>> +int board_eth_init(bd_t *bis)
>> +{
>> + int ret;
>> +
>> + setup_iomux_fec();
>> +
>> + ret = fecmxc_initialize_multi(bis, 0,
>> + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>> + if (ret)
>> + printf("FEC1 MXC: %s:failed\n", __func__);
>> +
>> + return ret;
>> +}
>> +
>> +static int setup_fec(void)
>> +{
>> + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
>> + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>> +
>> +#ifndef CONFIG_COLIBRI_EXT_PHYCLK
>
> Ditto.
It's the same config, but yes, will move it to Kconfig.
--
Stefan
>
>> + /*
>> + * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
>> + * and output it on the pin
>> + */
>> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
>> + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
>> + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
>> +#else
>> + /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
>> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
>> + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
>> + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
>> +#endif
>> +
>> + return set_clk_enet(ENET_50MHz);
>> +}
>> +
>> +int board_phy_config(struct phy_device *phydev)
>> +{
>> + if (phydev->drv->config)
>> + phydev->drv->config(phydev);
>> + return 0;
>> +}
>> +#endif
>> +
>> +int board_early_init_f(void)
>> +{
>> + setup_iomux_uart();
>> +
>> +#ifdef CONFIG_SYS_I2C_MXC
>> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
>> + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + /* address of boot parameters */
>> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>> +
>> +#ifdef CONFIG_FEC_MXC
>> + setup_fec();
>> +#endif
>> +
>> +#ifdef CONFIG_NAND_MXS
>> + setup_gpmi_nand();
>> +#endif
>> +
>> +#ifdef CONFIG_VIDEO_MXS
>> + setup_lcd();
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_CMD_BMODE
>> +static const struct boot_mode board_boot_modes[] = {
>> + /* 4 bit bus width */
>> + {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
>> + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
>> + {NULL, 0},
>> +};
>> +#endif
>> +
>> +int board_late_init(void)
>> +{
>> +#ifdef CONFIG_CMD_BMODE
>> + add_board_boot_modes(board_boot_modes);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +int checkboard(void)
>> +{
>> + printf("Model: Toradex Colibri iMX7%c\n",
>> + is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_USB_EHCI_MX7
>> +static iomux_v3_cfg_t const usb_otg2_pads[] = {
>> + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +int board_ehci_hcd_init(int port)
>> +{
>> + switch (port) {
>> + case 0:
>> + break;
>> + case 1:
>> + if (is_cpu_type(MXC_CPU_MX7S))
>> + return -ENODEV;
>> +
>> + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
>> + ARRAY_SIZE(usb_otg2_pads));
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> + return 0;
>> +}
>> +#endif
>> +
>> +static struct mxc_serial_platdata mxc_serial_plat = {
>> + .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
>> + .use_dte = true,
>> +};
>> +
>> +U_BOOT_DEVICE(mxc_serial) = {
>> + .name = "serial_mxc",
>> + .platdata = &mxc_serial_plat,
>> +};
>> diff --git a/board/toradex/colibri_imx7/imximage.cfg
>> b/board/toradex/colibri_imx7/imximage.cfg
>> new file mode 100644
>> index 0000000..d891e82
>> --- /dev/null
>> +++ b/board/toradex/colibri_imx7/imximage.cfg
>> @@ -0,0 +1,150 @@
>> +/*
>> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
>> + * 2015 Toradex AG
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + * Refer docs/README.imxmage for more details about how-to configure
>> + * and create imximage boot image
>> + *
>> + * The syntax is taken as close as possible with the kwbimage
>> + */
>> +
>> +#define __ASSEMBLY__
>> +#include <config.h>
>> +
>> +/* image version */
>> +
>> +IMAGE_VERSION 2
>> +
>> +/*
>> + * Boot Device : sd
>> + */
>> +
>> +BOOT_FROM sd
>> +
>> +/*
>> + * Secure boot support
>> + */
>> +#ifdef CONFIG_SECURE_BOOT
>> +CSF CONFIG_CSF_SIZE
>> +#endif
>> +
>> +/*
>> + * Device Configuration Data (DCD)
>> + *
>> + * Each entry must have the format:
>> + * Addr-type Address Value
>> + *
>> + * where:
>> + * Addr-type register length (1,2 or 4 bytes)
>> + * Address absolute address of the register
>> + * value value to be stored in the register
>> + */
>> +
>> +/* IOMUXC_GPR_GPR1 */
>> +DATA 4 0x30340004 0x4F400005
>> +
>> +/* DDR3L */
>> +/* assuming MEMC_FREQ_RATIO = 2 */
>> +/* SRC_DDRC_RCR */
>> +DATA 4 0x30391000 0x00000002
>> +/* DDRC_MSTR */
>> +DATA 4 0x307a0000 0x01040001
>> +/* DDRC_DFIUPD0 */
>> +DATA 4 0x307a01a0 0x80400003
>> +/* DDRC_DFIUPD1 */
>> +DATA 4 0x307a01a4 0x00100020
>> +/* DDRC_DFIUPD2 */
>> +DATA 4 0x307a01a8 0x80100004
>> +/* DDRC_RFSHTMG */
>> +DATA 4 0x307a0064 0x00400045
>> +/* DDRC_MP_PCTRL_0 */
>> +DATA 4 0x307a0490 0x00000001
>> +/* DDRC_INIT0 */
>> +DATA 4 0x307a00d0 0x00020083
>> +/* DDRC_INIT1 */
>> +DATA 4 0x307a00d4 0x00690000
>> +/* DDRC_INIT3 MR0/MR1 */
>> +DATA 4 0x307a00dc 0x09300004
>> +/* DDRC_INIT4 MR2/MR3 */
>> +DATA 4 0x307a00e0 0x04480000
>> +/* DDRC_INIT5 */
>> +DATA 4 0x307a00e4 0x00100004
>> +/* DDRC_RANKCTL */
>> +DATA 4 0x307a00f4 0x0000033f
>> +/* DDRC_DRAMTMG0 */
>> +DATA 4 0x307a0100 0x090b090a
>> +/* DDRC_DRAMTMG1 */
>> +DATA 4 0x307a0104 0x000d020d
>> +/* DDRC_DRAMTMG2 */
>> +DATA 4 0x307a0108 0x03040307
>> +/* DDRC_DRAMTMG3 */
>> +DATA 4 0x307a010c 0x00002006
>> +/* DDRC_DRAMTMG4 */
>> +DATA 4 0x307a0110 0x04020205
>> +/* DDRC_DRAMTMG5 */
>> +DATA 4 0x307a0114 0x03030202
>> +/* DDRC_DRAMTMG8 */
>> +DATA 4 0x307a0120 0x00000803
>> +/* DDRC_ZQCTL0 */
>> +DATA 4 0x307a0180 0x00800020
>> +/* DDRC_ZQCTL1 */
>> +DATA 4 0x307a0184 0x02001000
>> +/* DDRC_DFITMG0 */
>> +DATA 4 0x307a0190 0x02098204
>> +/* DDRC_DFITMG1 */
>> +DATA 4 0x307a0194 0x00030303
>> +/* DDRC_ADDRMAP0 */
>> +DATA 4 0x307a0200 0x0000001f
>> +/* DDRC_ADDRMAP1 */
>> +DATA 4 0x307a0204 0x00080808
>> +/* DDRC_ADDRMAP5 */
>> +DATA 4 0x307a0214 0x07070707
>> +/* DDRC_ADDRMAP6 */
>> +DATA 4 0x307a0218 0x07070707
>> +/* DDRC_ODTCFG */
>> +DATA 4 0x307a0240 0x06000601
>> +/* DDRC_ODTMAP */
>> +DATA 4 0x307a0244 0x00000011
>> +/* SRC_DDRC_RCR */
>> +DATA 4 0x30391000 0x00000000
>> +/* DDR_PHY_PHY_CON0 */
>> +DATA 4 0x30790000 0x17420f40
>> +/* DDR_PHY_PHY_CON1 */
>> +DATA 4 0x30790004 0x10210100
>> +/* DDR_PHY_PHY_CON4 */
>> +DATA 4 0x30790010 0x00060807
>> +/* DDR_PHY_MDLL_CON0 */
>> +DATA 4 0x307900b0 0x1010007e
>> +/* DDR_PHY_DRVDS_CON0 */
>> +DATA 4 0x3079009c 0x00000d6e
>> +/* DDR_PHY_OFFSET_RD_CON0 */
>> +DATA 4 0x30790020 0x08080808
>> +/* DDR_PHY_OFFSET_WR_CON0 */
>> +DATA 4 0x30790030 0x08080808
>> +/* DDR_PHY_CMD_SDLL_CON0 */
>> +DATA 4 0x30790050 0x01000010
>> +DATA 4 0x30790050 0x00000010
>> +
>> +/* DDR_PHY_ZQ_CON0 */
>> +DATA 4 0x307900c0 0x0e407304
>> +DATA 4 0x307900c0 0x0e447304
>> +DATA 4 0x307900c0 0x0e447306
>> +/* DDR_PHY_ZQ_CON1 */
>> +CHECK_BITS_SET 4 0x307900c4 0x1
>> +/* DDR_PHY_ZQ_CON0 */
>> +DATA 4 0x307900c0 0x0e447304
>> +DATA 4 0x307900c0 0x0e407304
>> +
>> +/* CCM_CCGRn */
>> +DATA 4 0x30384130 0x00000000
>> +/* IOMUXC_GPR_GPR8 */
>> +DATA 4 0x30340020 0x00000178
>> +/* CCM_CCGRn */
>> +DATA 4 0x30384130 0x00000002
>> +/* DDR_PHY_LP_CON0 */
>> +DATA 4 0x30790018 0x0000000f
>> +
>> +/* DDRC_STAT */
>> +CHECK_BITS_SET 4 0x307a0004 0x1
>> diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
>> new file mode 100644
>> index 0000000..50c1201
>> --- /dev/null
>> +++ b/configs/colibri_imx7_defconfig
>> @@ -0,0 +1,40 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_MX7=y
>> +CONFIG_TARGET_COLIBRI_IMX7=y
>> +CONFIG_IMX_RDC=y
>> +CONFIG_IMX_BOOTAUX=y
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
>> +CONFIG_BOOTDELAY=1
>> +CONFIG_HUSH_PARSER=y
>> +CONFIG_SYS_PROMPT="Colibri iMX7 # "
>> +# CONFIG_CMD_BOOTD is not set
>> +CONFIG_CMD_BOOTZ=y
>> +# CONFIG_CMD_IMI is not set
>> +# CONFIG_CMD_IMLS is not set
>> +# CONFIG_CMD_XIMG is not set
>> +CONFIG_CMD_ASKENV=y
>> +CONFIG_CMD_MEMTEST=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_NAND=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_DFU=y
>> +CONFIG_CMD_USB_MASS_STORAGE=y
>> +# CONFIG_CMD_FPGA is not set
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_DHCP=y
>> +CONFIG_CMD_MII=y
>> +CONFIG_CMD_PING=y
>> +CONFIG_CMD_CACHE=y
>> +CONFIG_CMD_EXT4=y
>> +CONFIG_CMD_FAT=y
>> +CONFIG_CMD_FS_GENERIC=y
>> +CONFIG_USB=y
>> +CONFIG_USB_EHCI_HCD=y
>> +CONFIG_USB_GADGET=y
>> +CONFIG_CI_UDC=y
>> +CONFIG_USB_GADGET_DOWNLOAD=y
>> +CONFIG_G_DNL_MANUFACTURER="Toradex"
>> +CONFIG_G_DNL_VENDOR_NUM=0x1b67
>> +CONFIG_G_DNL_PRODUCT_NUM=0x4020
>> +CONFIG_OF_LIBFDT=y
>> diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
>> new file mode 100644
>> index 0000000..6dc429b
>> --- /dev/null
>> +++ b/include/configs/colibri_imx7.h
>> @@ -0,0 +1,248 @@
>> +/*
>> + * Copyright 2016 Toradex AG
>> + *
>> + * Configuration settings for the Colibri iMX7 module.
>> + *
>> + * based on mx7dsabresd.h:
>> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __COLIBRI_IMX7_CONFIG_H
>> +#define __COLIBRI_IMX7_CONFIG_H
>> +
>> +#include "mx7_common.h"
>> +
>> +#define CONFIG_SYS_THUMB_BUILD
>> +#define CONFIG_USE_ARCH_MEMCPY
>> +#define CONFIG_USE_ARCH_MEMSET
>> +
>> +/*#define CONFIG_DBG_MONITOR*/
>> +#define PHYS_SDRAM_SIZE SZ_512M
>> +
>> +#define CONFIG_BOARD_EARLY_INIT_F
>> +#define CONFIG_BOARD_LATE_INIT
>> +
>> +#define CONFIG_DISPLAY_BOARDINFO_LATE
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
>> +
>> +/* Uncomment to enable secure boot support */
>> +/* #define CONFIG_SECURE_BOOT */
>> +#define CONFIG_CSF_SIZE 0x4000
>> +
>> +#define CONFIG_CMD_BMODE
>> +
>> +/* Network */
>> +#define CONFIG_COLIBRI_EXT_PHYCLK
>> +#define CONFIG_FEC_MXC
>> +#define CONFIG_MII
>> +#define CONFIG_FEC_XCV_TYPE RMII
>> +#define CONFIG_ETHPRIME "FEC"
>> +#define CONFIG_FEC_MXC_PHYADDR 0
>> +
>> +#define CONFIG_PHYLIB
>> +#define CONFIG_PHY_MICREL
>> +#define CONFIG_TFTP_TSIZE
>> +#define CONFIG_IP_DEFRAG
>> +#define CONFIG_TFTP_BLOCKSIZE 16384
>> +
>> +/* ENET1 */
>> +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
>> +
>> +/* MMC Config*/
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
>> +#define CONFIG_SYS_FSL_USDHC_NUM 1
>> +
>> +#undef CONFIG_BOOTM_PLAN9
>> +#undef CONFIG_BOOTM_RTEMS
>> +
>> +/* I2C configs */
>> +#define CONFIG_SYS_I2C
>> +#define CONFIG_SYS_I2C_MXC
>> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
>> +#define CONFIG_SYS_I2C_SPEED 100000
>> +
>> +#define CONFIG_IPADDR 192.168.10.2
>> +#define CONFIG_NETMASK 255.255.255.0
>> +#define CONFIG_SERVERIP 192.168.10.1
>> +
>> +#define MEM_LAYOUT_ENV_SETTINGS \
>> + "fdt_addr_r=0x82000000\0" \
>> + "fdt_high=0xffffffff\0" \
>> + "initrd_high=0xffffffff\0" \
>> + "kernel_addr_r=0x81000000\0" \
>> + "ramdisk_addr_r=0x82100000\0"
>> +
>> +#define SD_BOOTCMD \
>> + "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \
>> + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
>> + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
>> + "run m4boot && " \
>> + "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
>> + "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
>> + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>> +
>> +#define NFS_BOOTCMD \
>> + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
>> + "nfsboot=run setup; " \
>> + "setenv bootargs ${defargs} ${nfsargs} " \
>> + "${setupargs} ${vidargs}; echo Booting from NFS...;" \
>> + "dhcp ${kernel_addr_r} && " \
>> + "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
>> + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>> +
>> +#define UBI_BOOTCMD \
>> + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
>> + "ubi.fm_autoconvert=1\0" \
>> + "ubiboot=run setup; " \
>> + "setenv bootargs ${defargs} ${ubiargs} " \
>> + "${setupargs} ${vidargs}; echo Booting from NAND...; " \
>> + "ubi part ubi && run m4boot && " \
>> + "ubi read ${kernel_addr_r} kernel && " \
>> + "ubi read ${fdt_addr_r} dtb && " \
>> + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>> +
>> +#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + MEM_LAYOUT_ENV_SETTINGS \
>> + NFS_BOOTCMD \
>> + SD_BOOTCMD \
>> + UBI_BOOTCMD \
>> + "console=ttymxc0\0" \
>> + "defargs=\0" \
>> + "fdt_board=eval-v3\0" \
>> + "fdt_fixup=;\0" \
>> + "m4boot=;\0" \
>> + "ip_dyn=yes\0" \
>> + "kernel_file=zImage\0" \
>> + "mtdparts=" MTDPARTS_DEFAULT "\0" \
>> + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
>> + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
>> + "${board}/flash_eth.img && source ${loadaddr}\0" \
>> + "setsdupdate=mmc rescan && setenv interface mmc && " \
>> + "fatload ${interface} 0:1 ${loadaddr} " \
>> + "${board}/flash_blk.img && source ${loadaddr}\0" \
>> + "setup=setenv setupargs " \
>> + "console=tty1 console=${console}" \
>> + ",${baudrate}n8 ${memargs} consoleblank=0 ${mtdparts}\0" \
>> + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
>> + "setusbupdate=usb start && setenv interface usb && " \
>> + "fatload ${interface} 0:1 ${loadaddr} " \
>> + "${board}/flash_blk.img && source ${loadaddr}\0" \
>> + "splashpos=m,m\0" \
>> +
>> "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0"
>> \
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_LONGHELP
>> +
>> +#define CONFIG_SYS_MEMTEST_START 0x80000000
>> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START +
>> 0x0c000000)
>> +
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +#define CONFIG_SYS_HZ 1000
>> +
>> +#define CONFIG_STACKSIZE SZ_128K
>> +
>> +/* Physical Memory Map */
>> +#define CONFIG_NR_DRAM_BANKS 1
>> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
>> +
>> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
>> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
>> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
>> +
>> +#define CONFIG_SYS_INIT_SP_OFFSET \
>> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_ADDR \
>> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>> +
>> +/* FLASH and environment organization */
>> +#define CONFIG_SYS_NO_FLASH
>> +#define CONFIG_ENV_IS_IN_NAND
>> +
>> +#if defined(CONFIG_ENV_IS_IN_MMC)
>> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
>> +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
>> +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
>> +#define CONFIG_ENV_OFFSET (8 * SZ_64K)
>> +#elif defined(CONFIG_ENV_IS_IN_NAND)
>> +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
>> +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
>> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
>> +#endif
>> +
>> +#define CONFIG_NAND_MXS
>> +#define CONFIG_CMD_NAND_TRIMFFS
>> +
>> +/* NAND stuff */
>> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
>> +#define CONFIG_SYS_NAND_BASE 0x40000000
>> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
>> +#define CONFIG_SYS_NAND_ONFI_DETECTION
>> +#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
>> +#define CONFIG_CMD_NAND_TORTURE
>> +
>> +/* UBI stuff */
>> +#define CONFIG_RBTREE
>> +#define CONFIG_LZO
>> +#define CONFIG_CMD_UBI
>> +#define CONFIG_MTD_UBI_FASTMAP
>> +#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
>> +
>> +/* Dynamic MTD partition support */
>> +#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
>> +#define CONFIG_MTD_PARTITIONS
>> +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
>> +#define MTDIDS_DEFAULT "nand0=gpmi-nand"
>> +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:" \
>> + "512k(mx7-bcb)," \
>> + "3584k(u-boot)ro," \
>> + "512k(u-boot-env)," \
>> + "-(ubi)"
>> +
>> +/* DMA stuff, needed for GPMI/MXS NAND support */
>> +#define CONFIG_APBH_DMA
>> +#define CONFIG_APBH_DMA_BURST
>> +#define CONFIG_APBH_DMA_BURST8
>> +
>> +/* USB Configs */
>> +#define CONFIG_USB_STORAGE
>> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>> +
>> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
>> +#define CONFIG_MXC_USB_FLAGS 0
>> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>> +
>> +#define CONFIG_IMX_THERMAL
>> +
>> +#define CONFIG_USBD_HS
>> +
>> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
>> +
>> +/* USB Device Firmware Update support */
>> +#define CONFIG_USB_FUNCTION_DFU
>> +#define CONFIG_DFU_MMC
>> +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
>> +#define DFU_DEFAULT_POLL_TIMEOUT 300
>> +
>> +#define CONFIG_VIDEO
>> +#ifdef CONFIG_VIDEO
>> +#define CONFIG_CFB_CONSOLE
>> +#define CONFIG_VIDEO_MXS
>> +#define CONFIG_VIDEO_LOGO
>> +#define CONFIG_VIDEO_SW_CURSOR
>> +#define CONFIG_VGA_AS_SINGLE_DEVICE
>> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
>> +#define CONFIG_SPLASH_SCREEN
>> +#define CONFIG_SPLASH_SCREEN_ALIGN
>> +#define CONFIG_CMD_BMP
>> +#define CONFIG_BMP_16BPP
>> +#define CONFIG_VIDEO_BMP_RLE8
>> +#define CONFIG_VIDEO_BMP_LOGO
>> +#endif
>> +
>> +#endif
>>
>
> Best regards,
> Stefano Babic
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