Hello
In the sdram_config.h files for the ARM SoC (Arria5 and Cyclone5):
- board/altera/cyclone5-socdk/qts/sdram_config.h
- board/altera/arria5-socdk/qts/sdram_config.h
There are 2 values for self-refresh exit and power-down exit DRAM timing:
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
I think those 2 values are inverted. The DRAM documents specify that
the self-refresh exit shall be something along the lines 'Greatest of
5CK or tRFC (which is the refresh cycle period)'. The tRFC requirement
is so that if self-refresh mode is exit from at the instant a row
refresh was self-initiated, that the operation has time to complete
before resuming other operations. That is the time to delay when not
requiring the DLL to re-lock. And the power-down exit is the delay to
give when the DLL has to re-lock (since DRAM was in power-down), and
minimum value is tDLL (usually 512CK).
So, the two values seem to be inverted, right?
I know where the confusion comes from though, as while investigating the
issue, I found out that the Quartus QSYS does give those inverted
values. That's right, there seem to be a bug in Altera's QSYS, and it's
been there since probably forever. I have opened a request with Altera
mySupport in parallel, to ask and confirm if there is indeed a bug in QSYS.
So, the files should read:
...
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
...
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 139
Can you confirm the issue?
Best regards,
Eric
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