On 27 July 2016 at 15:48, Stephen Warren <swar...@wwwdotorg.org> wrote: > From: Stephen Warren <swar...@nvidia.com> > > The Tegra186 PCIe DT content is almost identical to previous chips, except > that the: > > - There are 3 ports instead of 2. > - Some physical addresses have moved. > - PHY programming is handled by firmware, so CCPLEX DTs don't need to > reference any PHY. > - The power domain is explicitly represented in DT. This change is > mandatory for Tegra186 since standard power domain APIs are used, and > should be made to the DT for older SoCs, although we get away without > doing so since U-Boot currently uses custom APIs that hard-code power > domain IDs. > > Signed-off-by: Stephen Warren <swar...@nvidia.com> > --- > arch/arm/dts/tegra186.dtsi | 92 > ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+)
Reviewed-by: Simon Glass <s...@chromium.org> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
