From: Stefan Agner <stefan.ag...@toradex.com>
Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
---
Changes in v5:
- Add this LPAE enablement patch
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/lib/cache-cp15.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3..3aabda1 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,7 +61,11 @@ __weak void mmu_page_table_flush(unsigned long start,
unsigned long stop)
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
+#ifdef CONFIG_ARMV7_LPAE
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
+#endif
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
--
2.9.0
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