Hi Fred, Thank you for your fast reply, please see my comments below:
On 9/21/09, Fred Fan <fanyef...@gmail.com> wrote: > Dear Alan Carvalho de Assis, > > 2009/9/16 Alan Carvalho de Assis <acas...@gmail.com> > >> + /* >> + * DDR on CSD0 >> + */ >> + write32 0xD8001010, 0x00000008 >> + write32 0x10027828, 0x55555555 >> + write32 0x10027830, 0x55555555 >> + write32 0x10027834, 0x55555555 >> + write32 0x10027838, 0x00005005 >> + write32 0x1002783C, 0x15555555 >> + write32 0xD8001010, 0x00000004 >> + write32 0xD8001004, 0x006ac73a >> + write32 0xD8001000, 0x92100000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xD8001000, 0xA2100000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xD8001000, 0xA2200000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xA0000F00, 0x00000000 >> + write32 0xD8001000, 0xb2100000 > > + ldr r0, =0xA0000033 >> + mov r1, #0xda >> + strb r1, [r0] >> + ldr r0, =0xA1000000 >> + mov r1, #0xff >> + strb r1, [r0] >> + write32 0xD8001000, 0x82226080 > > Please use the friendly register definition. I based on U-Boot-v2 start-up code. Where should I place these registers definition? (could be in include/asm-arm/arch-mx27/imx-regs.h ?) >> + * >> + * FIXME: Using the 399*2 MHz values from table 3-8 doens't work >> + * with 1.2 V core voltage! Find out if this is >> + * documented somewhere. >> + */ >> + write32 MPCTL0, 0x1EF15D5 /* MPLL = 199.5*2 MHz >> */ >> + write32 SPCTL0, 0x043A1C09 /* SPLL = FIXME (needs review) >> */ >> > I will check the setting in another mail. > Sure, I will wait for it. >> + /* clock gating enable */ >> + write32 0x10027818, 0x00050f08 >> + >> > ditto > ACK >> + >> + /* skip sdram initialization if we run from ram */ >> + cmp pc, #0xa0000000 >> + bls 1f >> + cmp pc, #0xc0000000 >> + bhi 1f >> > Please use the definitions of ddr area. > Ok >> +int board_init(void) >> +{ >> + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; >> + >> + gd->bd->bi_arch_number = MACH_TYPE_MX27ADS; >> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; >> > move bi_boot_params to dram_init. > Ok >> +/* >> + * Ethernet >> + */ >> +#define CONFIG_FEC_MXC >> +#define CONFIG_FEC_MXC_PHYADDR 0x1f >> +#define CONFIG_MII >> +#define CONFIG_NET_MULTI >> + >> +/*#define CONFIG_DRIVER_CS8900 1 >> +#define CS8900_BASE 0xD4020300 >> +#define CS8900_BUS16 1*/ >> > Remove commented code. > I will active this commented lines, I think it just need another ETHADDR to work. >> +#define CONFIG_ETHADDR 02:80:ad:20:31:e8 Thank you Fred, I am glad to see more Freescale guys helping open-source projects. Best Regards, Alan _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot